ICS8521BYI IDT, Integrated Device Technology Inc, ICS8521BYI Datasheet - Page 9

• Manufacturer Part Number: ICS8521BYI
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of ICS8521BYI

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 500MHz
• Output Logic Level: HSTL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: LQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Not Compliant

IDT™ / ICS™ LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
ICS8521I
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
F
8521BYI
LVPECL C
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V
and V
face examples for the HiPerClockS PCLK/nPCLK input driven
by the most common driver types. The input interfaces sug-
F
F
IGURE
IGURE
IGURE
3.3V
CMR
3.3V
4C. H
4E. H
4A. H
3.3V LVPECL
3.3V
input requirements. Figures 4A to 4D show inter-
LVPECL
CML
R5
100 - 200
BY A
BY A
BY A
LOCK
I
I
I
P
P
P
Integrated
Circuit
Systems, Inc.
ER
ER
ER
Zo = 50 Ohm
Zo = 50 Ohm
3.3V LVPECL D
3.3V LVPECL D
CML D
R6
100 - 200
C
C
C
I
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
LOCK
LOCK
LOCK
NPUT
S PCLK/
S PCLK/
S PCLK/
RIVER
SWING
I
NTERFACE
C1
C2
3.3V
R3
125
3.3V
R1
50
and V
R1
84
3.3V
R3
84
N
R2
50
N
RIVER WITH
N
RIVER
R1
125
R4
125
PCLK I
PCLK I
PCLK I
R2
84
OH
PCLK
nPCLK
R4
84
R2
125
must meet the V
3.3V
www.icst.com/products/hiperclocks.html
CLK
nCLK
3.3V
HiPerClockS
PCLK/nPCLK
NPUT
NPUT
NPUT
PCLK
nPCLK
HiPerClockS
Input
AC C
3.3V
D
D
D
HiPerClockS
PCLK/nPCLK
RIVEN
RIVEN
RIVEN
OUPLE
PP
9
9
gested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please con-
sult with the vendor of the driver component to confirm the
driver termination requirements.
F
F
IGURE
IGURE
D
3.3V
IFFERENTIAL
4D. H
LVDS_Driv er
4B. H
2.5V
SSTL
BY A
BY AN
I
I
P
P
ER
ER
3.3V LVDS D
C
Zo = 60 Ohm
Zo = 60 Ohm
C
SSTL D
LOCK
LOCK
Zo = 50 Ohm
Zo = 50 Ohm
-
TO
S PCLK/
S PCLK/
-HSTL F
RIVER
2.5V
R3
120
R1
120
RIVER
L
R4
120
OW
R2
120
N
N
R1
100
PCLK I
PCLK I
ANOUT
S
PCLK
nPCLK
REV. A NOVEMBER 17, 2005
3.3V
KEW
NPUT
NPUT
HiPerClockS
PCLK/nPCLK
CLK
nCLK
3.3V
, 1-
B
Receiv er
D
D
UFFER
RIVEN
RIVEN
TO
ICS8521I
-9
TSD