ICS85310AYI-11 IDT, Integrated Device Technology Inc, ICS85310AYI-11 Datasheet - Page 6

• Manufacturer Part Number: ICS85310AYI-11
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of ICS85310AYI-11

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 700MHz
• Output Logic Level: ECL/LVPECL
• Operating Supply Voltage (min): -2.375/2.375V
• Operating Supply Voltage (typ): -2.5/-3.3/3.3V
• Operating Supply Voltage (max): -3.8/3.8V
• Package Type: LQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Not Compliant

ICS85310I-11 Data Sheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
ICS85310AYI-11 REVISION F JUNE 9, 2010
Offset from Carrier Frequency (Hz)
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL FANOUT BUFFER
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of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
@ 155.52MHz = <0.13ps (typical)
Additive Phase Jitter, RMS
©2010 Integrated Device Technology, Inc.