ICS853052AGT IDT, Integrated Device Technology Inc, ICS853052AGT Datasheet - Page 5

• Manufacturer Part Number: ICS853052AGT
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Multiplexerr

Specifications of ICS853052AGT

• Number Of Clock Inputs: 2
• Mode Of Operation: Single-Ended
• Output Logic Level: LVPECL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: LVCMOS/LVTTL
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Not Compliant

IDT
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
ICS853052
DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
™
/ ICS
™
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
100
1k
A
O
10k
FFSET
DDITIVE
F
ROM
P
C
HASE
5
ARRIER
100k
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
J
F
ITTER
REQUENCY
Additive Phase Jitter
(12kHz to 20MHz) = 0.06ps typical
(H
1M
Z
)
ICS853052AG REV. B JANUARY 16, 2008
10M
@ 155.52MHz
PRELIMINARY
100M