ICS8536AG-02T IDT, Integrated Device Technology Inc, ICS8536AG-02T Datasheet - Page 7

• Manufacturer Part Number: ICS8536AG-02T
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of ICS8536AG-02T

• Number Of Clock Inputs: 3
• Mode Of Operation: Single-Ended
• Output Frequency: 266MHz
• Output Logic Level: LVPECL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Signal Type: LVCMOS/LVTTL
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / RoHS Status: Compliant

ICS8536-02 Data Sheet
ICS8536AG-02 REVISION A JULY 21, 2010
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a Phase
noise plot and is most often the specified plot in many applications.
Phase noise is defined as the ratio of the noise power present in a
1Hz band at a specified offset from the fundamental frequency to
the power value of the fundamental. This ratio is expressed in
decibels (dBm) or a ratio of the power in the 1Hz band to the power
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device.
This is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Offset from Carrier Frequency (Hz)
7
in the fundamental. When the required offset is specified, the phase
noise is called a dBc value, which simply means dBm at a specified
offset from the fundamental. By investigating jitter in the frequency
domain, we get a better understanding of its effects on the desired
application over the entire time record of the signal. It is
mathematically possible to calculate an expected bit error rate given
a phase noise plot.
The source generator "SMA 100 Generator 9kHz – 6GHz as
external input to an Agilent 8133A 3HGz Pulse Generator”.
1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
12kHz to 20MHz = 0.149ps (typical)
©2010 Integrated Device Technology, Inc.
RMS Phase Jitter (Random)
155.52MHz