ICS87946AYI-01T IDT, Integrated Device Technology Inc, ICS87946AYI-01T Datasheet
ICS87946AYI-01T
Specifications of ICS87946AYI-01T
Related parts for ICS87946AYI-01T
ICS87946AYI-01T Summary of contents
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... Pullup nPCLK ÷2 Pulldown DIV_SELA Pulldown DIV_SELB Pulldown DIV_SELC Pulldown MR/nOE ICS87946AYI-01 REVISION B NOVEMBER 10, 2009 LVPECL-To-LVCMOS/LVTTL ÷1, ÷2 Features • Ten single ended LVCMOS/LVTTL outputs, 7Ω typical output impedance • LVPECL clock input pair • PCLK/nPCLK supports the following input levels: LVPECL, CML, SSTL • ...
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... C Power Dissipation Capacitance PD R Input Pullup Resistor PULLUP R Input Pulldown Resistor PULLDOWN R Output Impedance OUT ICS87946AYI-01 REVISION B NOVEMBER 10, 2009 Type Description Unused No connect. Power Power supply pin. Input Pulldown Non-inverting differential LVPECL clock input. Input Pullup Inverting differential LVPECL clock input. ...
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... Parameter V Positive Supply Voltage Output Supply Voltage DDA, DDB, DDC I Power Supply Current Output Supply Current DDA, DDB, DDC ICS87946AYI-01 REVISION B NOVEMBER 10, 2009 LOW SKEW, ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR DIV_SELC QA0:QA2 X X High-Impedance X X fIN fIN Active 1 X Active X 0 Active ...
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... Input High Current IH nPCLK PCLK I Input Low Current IL nPCLK V Peak-to-Peak Voltage PP V Common Mode Input Voltage; NOTE 1 CMR NOTE 1: Common mode input voltage is defined as V ICS87946AYI-01 REVISION B NOVEMBER 10, 2009 = 3.3V ± 5 DDA Test Conditions = -40°C to 85°C A Test Conditions V = 3.465V 3.465V ...
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... Output Rise/Fall Time R F odc Output Duty Cycle t Output Enable Time; NOTE Output Disable Time; NOTE 6 DIS For NOTES, please see Table 5A above. ICS87946AYI-01 REVISION B NOVEMBER 10, 2009 = 3.3V ± 5 DDA DDB DDC Test Conditions ƒ ≤ 250MHz Measured on rising edge at V Measured on rising edge at V ...
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... Often the noise floor of the equipment is higher than the noise floor of the device. This ICS87946AYI-01 REVISION B NOVEMBER 10, 2009 LOW SKEW, ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental ...
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... Cross Points PP PCLK GND Differential Input Level V DDx 2 QX0:QXx V DDx 2 QX0:QXx tsk(b) Where X = Bank Bank Skew ICS87946AYI-01 REVISION B NOVEMBER 10, 2009 LOW SKEW, ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR 2.05V¬±5 SCOPE LVCMOS 3.3V/2.5V Output Load AC Test Circuit Qx V CMR Qy Output Skew ...
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... Part 2 V DDO Qy 2 tsk(pp) Part-to-Part Skew 80% QAx, 20% QBx, QCx t R Output Rise/Fall Time ICS87946AYI-01 REVISION B NOVEMBER 10, 2009 LOW SKEW, ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR nPCLK PCLK QAx, QBx, QCx Propagation Delay QAx, QBx, QCx 80% 20 Output Duty Cycle/Pulse Width/Period 8 V DDx ...
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... For example, if the input clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V and R2/ 0.609. ICS87946AYI-01 REVISION B NOVEMBER 10, 2009 LOW SKEW, ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR Outputs: LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached ...
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... SSTL R1 120 Figure 2E. PCLK/nPCLK Input Driven by an SSTL Driver ICS87946AYI-01 REVISION B NOVEMBER 10, 2009 The input interfaces suggested here are examples only. If the driver and is from another vendor, use their termination recommendation. PP Please consult with the vendor of the driver component to confirm the driver termination requirements ...
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... Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Transistor Count The transistor count for ICS87946I-01 is: 1204 ICS87946AYI-01 REVISION B NOVEMBER 10, 2009 LOW SKEW, ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR θ vs. Air Flow ...
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... Basic D2 & E2 5.60 Ref. e 0.80 Basic L 0.45 0.60 θ 0° ccc Reference Document: JEDEC Publication 95, MS-026 ICS87946AYI-01 REVISION B NOVEMBER 10, 2009 LOW SKEW, ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR Maximum 1.60 0.15 1.45 0.45 0.20 0.75 7° 0.10 12 ©2009 Integrated Device Technology, Inc. ...
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... IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS87946AYI-01 REVISION B NOVEMBER 10, 2009 LOW SKEW, ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR Package ...
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... ICS87946AYI-01 REVISION B NOVEMBER 10, 2009 Description of Change Features section added Additive Phase Jitter and Lead-Free bullets AC Characteristics Tables - added Additive Phase Jitter row. Added Additive Phase Jitter section. Application Section - added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free Part/Order Number and Note. ...
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ICS87946I-01 6024 Silver Creek Valley Road Sales 800-345-7015 (inside USA) San Jose, California 95138 +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein ...