ICS87946AYI-01T IDT, Integrated Device Technology Inc, ICS87946AYI-01T Datasheet - Page 5

• Manufacturer Part Number: ICS87946AYI-01T
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Dividerr

Specifications of ICS87946AYI-01T

• Number Of Clock Inputs: 1
• Mode Of Operation: Differential
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: LQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Not Compliant

ICS87946I-01
AC Electrical Characteristics
Table 5A. AC Characteristics, V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to V
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltage and equal load conditions.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at V
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
Table 5B. AC Characteristics, V
For NOTES, please see Table 5A above.
ICS87946AYI-01 REVISION B NOVEMBER 10, 2009
Symbol
f
t
tsk(b)
tsk(o)
tsk(w)
tsk(pp)
tjit
t
odc
t
t
Symbol
f
t
tsk(b)
tsk(o)
tsk(w)
tsk(pp)
tjit
t
odc
t
t
MAX
PD
R
EN
DIS
MAX
PD
R
EN
DIS
/ t
/ t
F
F
Parameter
Output Frequency
Propagation Delay; NOTE 1
Bank Skew, NOTE 2, 7
Output Skew; NOTE 3, 7
Multiple Frequency Skew;
NOTE 4, 7
Part-to-Part Skew; NOTE 5, 7
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 6
Output Disable Time; NOTE 6
Parameter
Output Frequency
Propagation Delay; NOTE 1
Bank Skew, NOTE 2, 7
Output Skew; NOTE 3, 7
Multiple Frequency Skew;
NOTE 4, 7
Part-to-Part Skew; NOTE 5, 7
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 6
Output Disable Time; NOTE 6
DD
DD
= 3.3V ± 5%, V
= V
DDA
= V
Measured on rising edge at V
Measured on rising edge at V
Measured on rising edge at V
Measured on rising edge at V
Measured on rising edge at V
Measured on rising edge at V
Measured on rising edge at V
Measured on rising edge at V
DDB
= V
125MHz, 12kHz – 20MHz
125MHz, 12kHz – 20MHz
DDA
DDC
Test Conditions
= V
Test Conditions
20% to 80%
DDX
20% to 80%
ƒ ≤ 250MHz
ƒ ≤ 250MHz
ƒ = 10MHz
ƒ = 10MHz
ƒ = 10MHz
ƒ = 10MHz
DDB
= 3.3V ± 5%, T
/2 of the output.
= V
5
DDX
DDC
/2.
= 2.5V ± 5%, T
LOW SKEW, ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
A
= -40°C to 85°C
/2
/2
/2
/2
/2
/2
/2
/2
Minimum
Minimum
400
350
2.3
2.5
40
A
40
= -40°C to 85°C
©2009 Integrated Device Technology, Inc.
Typical
Typical
0.19
0.19
3.1
3.2
50
50
DDX
Maximum
Maximum
/2.
250
130
320
700
950
250
120
325
700
800
3.8
3.8
30
60
35
57
3
3
3
3
Units
Units
MHz
MHz
ns
ps
ps
ps
ps
ps
ps
ns
ns
ns
%
ps
ps
ps
ps
ps
ps
ns
ns
%