ICS87946AYI-01T IDT, Integrated Device Technology Inc, ICS87946AYI-01T Datasheet - Page 2

• Manufacturer Part Number: ICS87946AYI-01T
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Dividerr

Specifications of ICS87946AYI-01T

• Number Of Clock Inputs: 1
• Mode Of Operation: Differential
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: LQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Not Compliant

ICS87946I-01
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
ICS87946AYI-01 REVISION B NOVEMBER 10, 2009
Symbol
C
C
R
R
R
OUT
IN
PD
PULLUP
PULLDOWN
20, 24, 27, 31
8, 11, 15,
9, 13, 17
Number
10, 12,
19, 21,
26, 28,
14, 16
18, 22
25, 29
23
30
32
1
2
3
4
5
6
7
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
QC0, QC1,
DIV_SELA
DIV_SELB
DIV_SELC
QB2, QB1,
QA2, QA1,
QC2, QC3
MR/nOE
nPCLK
Name
PCLK
V
V
GND
V
QB0
QA0
V
nc
DDC
DDB
DDA
DD
Unused
Output
Output
Output
Power
Power
Power
Power
Power
Input
Input
Input
Input
Input
Input
Type
V
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
DD
Pullup
= V
DDA
Test Conditions
= V
Power supply pin.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
Controls frequency division for Bank A outputs. See Table 3
LVCMOS/LVTTL interface levels.
Controls frequency division for Bank B outputs. See Table 3.
LVCMOS/LVTTL interface levels.
Controls frequency division for Bank C outputs. See Table 3.
LVCMOS/LVTTL interface levels.
Power supply ground.
Output supply pins for Bank C outputs.
Single-ended Bank C clock outputs. LVCMOS/LVTTL interface levels.
7
Output supply pins for Bank B outputs.
Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels.
7
Output supply pins for Bank A outputs.
Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels.
7
Active HIGH Master Reset. Active LOW Output Enable. When logic HIGH,
the internal dividers are reset and the outputs are High-Impedance (Hi-Z).
When logic LOW, the internal dividers and the outputs are enabled. See
Table 3. LVCMOS/LVTTL interface levels.
Description
No connect.
Ω
Ω
Ω
DDB
typical output impedance.
typical output impedance.
typical output impedance.
2
= V
DDC
= 3.465V
LOW SKEW, ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Minimum
5
©2009 Integrated Device Technology, Inc.
Typical
51
51
4
7
Maximum
23
12
Units
k
k
pF
pF
Ω
Ω
Ω