PCF8573TD NXP Semiconductors, PCF8573TD Datasheet - Page 6

• Manufacturer Part Number: PCF8573TD
• Manufacturer: NXP Semiconductors

Specifications of PCF8573TD

• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 16
• Mounting: Surface Mount
• Time Format: HH:MM:SS
• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Table 1 Cycle length of the time counter
Note
1. During February of a leap-year the ‘Time Counter Days’ may be set to 29 by directly writing to it using the ‘execute
7.5
If the voltage V
operation of the clock becomes undefined. Therefore a
warning signal is required to indicate that faultless
operation of the clock is not guaranteed. This information
is latched in a flag called POWF (Power Fail) and remains
latched after restoration of the correct supply voltage until
a write sequence with EXECUTE ADDRESS has been
received. The flag POWF can be set by an internally
generated power fail level-discriminator signal for
applications with (V
externally generated power fail signal for applications with
(V
applied to the input PFIN. The input stage operates with
signals of slow rise and fall times. Internally or externally
controlled POWF can be selected by input EXTPF as
shown in Table 2.
Table 2 Power fail selection
Note
1. 0 = V
2003 Jan 27
minutes
hours
days
months
0
0
1
1
EXTPF
DD
Clock/calendar with serial I/O
address’ function. Leap-years must be tracked by the system software.
(1)
UNIT
Power on/power fail detection
V
(1)
SS1
SS1
) less than V
0
1
0
1
(LOW); 1 = V
PFIN
DD
7
6
6
5
DD
(1)
NUMBER OF BITS
V
SS1
V
TH1
power fail is sensed internally
test mode
power fail is sensed externally
no power fail sensed
falls below a certain value, the
SS1
DD
. The external signal must be
) greater than V
(HIGH).
FUNCTION
00 to 59
00 to 23
01 to 28
01 to 30
01 to 31
01 to 12
COUNTING CYCLE
TH1
, or by an
6
The external power fail control operates by absence of the
V
PFIN and EXTPF must be within the range V
A LOW level at PFIN indicates a power fail. POWF is
readable via the I
control is generated on-chip when the supply voltage
V
7.6
The level shifters adjust the 5 V operating voltage
(V
voltage (V
and counter are not influenced by the V
voltage. If the voltage V
the output signal of the level shifter is HIGH because V
is the common node of the V
supplies. Because the level shifters invert the input
signals, the internal circuit behaves as if a LOW signal is
present on the inputs. FSET, SEC, MIN and COMP are
CMOS push-pull output stages. The driving capability of
these outputs is lost when the supply voltage
V
DD
DD
DD
DD
59
23
28
or 29
30
31
12
V
V
V
Interface level shifters
V
SS2
SS2
SS2
FOLLOWING UNIT
SS2
DD
CARRY FOR
supply. Therefore the input levels applied to
is less than V
= 0.
) of the microcontroller to the internal supply
00
00
01
01
01
01
01
V
SS1
2
C-bus. A power-on reset for the I
) of the clock/calendar. The oscillator
DD
TH2
.
V
DD
SS2
2
2
4, 6, 9, 11
1, 3, 5, 7, 8, 10, 12
CONTENT OF MONTH
V
is absent (V
SS2
Product specification
COUNTER
and V
DD
PCF8573
V
DD
DD
SS2
DD
= V
V
supply
V
2
C-bus
SS1
SS1
SS2
.
DD
),