MR82C54/B Intersil, MR82C54/B Datasheet - Page 4

• Manufacturer Part Number: MR82C54/B
• Manufacturer: Intersil
• Type: Programmabler

Specifications of MR82C54/B

• # Internal Timers: Single
• Propagation Delay Time: 260ns
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Package Type: CLCC
• High Level Output Current: -2.5mA
• Low Level Output Current: 2.5mA
• Pin Count: 28
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Control Word Register
The Control Word Register (Figure 2) is selected by the
Read/Write Logic when A1, A0 = 11. If the CPU then does a
write operation to the 82C54, the data is stored in the Con-
trol Word Register and is interpreted as a Control Word used
to define the Counter operation.
The Control Word Register can only be written to; status
information is available with the Read-Back Command.
D
Counter 0, Counter 1, Counter 2
These three functional blocks are identical in operation, so
only a single Counter will be described. The internal block
diagram of a signal counter is shown in Figure 3. The
counters are fully independent. Each Counter may operate
in a different Mode.
The Control Word Register is shown in the figure; it is not
part of the Counter itself, but its contents determine how the
Counter operates.
The status register, shown in the figure, when latched, con-
tains the current contents of the Control Word Register and
status of the output and null count flag. (See detailed expla-
nation of the Read-Back command.)
The actual counter is labeled CE (for Counting Element). It is
a 16-bit presettable synchronous down counter.
7
FIGURE 2. CONTROL WORD REGISTER AND COUNTER
- D
WR
RD
CS
A
A
0
0
1
8
REGISTER
FUNCTIONS
CONTROL
BUFFER
WORD
WRITE
READ/
LOGIC
DATA/
BUS
COUNTER
COUNTER
COUNTER
0
1
2
CLK 0
GATE 0
OUT 0
CLK 1
GATE 1
OUT 1
CLK 2
GATE 2
OUT 2
82C54
4
CLK n
OLM and OLL are two 8-bit latches. OL stands for “Output
Latch”; the subscripts M and L for “Most significant byte” and
“Least significant byte”, respectively. Both are normally referred
to as one unit and called just OL. These latches normally “fol-
low” the CE, but if a suitable Counter Latch Command is sent to
the 82C54, the latches “latch” the present count until read by
the CPU and then return to “following” the CE. One latch at a
time is enabled by the counter’s Control Logic to drive the inter-
nal bus. This is how the 16-bit Counter communicates over the
8-bit internal bus. Note that the CE itself cannot be read; when-
ever you read the count, it is the OL that is being read.
Similarly, there are two 8-bit registers called CRM and CRL (for
“Count Register”). Both are normally referred to as one unit and
called just CR. When a new count is written to the Counter, the
count is stored in the CR and later transferred to the CE. The
Control Logic allows one register at a time to be loaded from
the internal bus. Both bytes are transferred to the CE simulta-
neously. CRM and CRL are cleared when the Counter is pro-
grammed for one byte counts (either most significant byte only
or least significant byte only) the other byte will be zero. Note
that the CE cannot be written into; whenever a count is written,
it is written into the CR.
The Control Logic is also shown in the diagram. CLK n,
GATE n, and OUT n are all connected to the outside world
through the Control Logic.
82C54 System Interface
The 82C54 is treated by the system software as an array of
peripheral I/O ports; three are counters and the fourth is a
control register for MODE programming.
Basically, the select inputs A0, A1 connect to the A0, A1
address bus signals of the CPU. The CS can be derived
directly from the address bus using a linear select method or
it can be connected to the output of a decoder.
REGISTER
CONTROL
CONTROL
GATE n
WORD
LOGIC
FIGURE 3. COUNTER INTERNAL BLOCK DIAGRAM
OUT n
REGISTER
STATUS
STATUS
LATCH
INTERNAL BUS
CR
OL
M
M
CE
CR
OL
L
L