MR82C54/B Intersil, MR82C54/B Datasheet - Page 9

• Manufacturer Part Number: MR82C54/B
• Manufacturer: Intersil
• Type: Programmabler

Specifications of MR82C54/B

• # Internal Timers: Single
• Propagation Delay Time: 260ns
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Package Type: CLCC
• High Level Output Current: -2.5mA
• Low Level Output Current: 2.5mA
• Pin Count: 28
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Both count and status of the selected counter(s) may be
latched simultaneously by setting both COUNT and STA-
TUS bits D5, D4 = 0. This is functionally the same as issuing
two separate read-back commands at once, and the above
discussions apply here also. Specifically, if multiple count
and/or status read-back commands are issued to the same
counter(s) without any intervening reads, all but the first are
ignored. This is illustrated in Figure 7.
If both count and status of a counter are latched, the first
read operation of that counter will return latched status,
regardless of which was latched first. The next one or two
reads (depending on whether the counter is programmed for
one or two type counts) return latched count. Subsequent
reads return unlatched count.
Mode Definitions
The following are defined for use in describing the operation
of the 82C54.
CLK PULSE:
A rising edge, then a falling edge, in that order, of a
Counter’s CLK input.
TRIGGER:
A rising edge of a Counter’s Gate input.
COUNTER LOADING:
The transfer of a count from the CR to the CE (See “Func-
tional Description”)
Mode 0: Interrupt on Terminal Count
Mode 0 is typically used for event counting. After the Control
Word is written, OUT is initially low, and will remain low until
the Counter reaches zero. OUT then goes high and remains
high until a new count or a new Mode 0 Control Word is writ-
ten to the Counter.
GATE = 1 enables counting; GATE = 0 disables counting.
GATE has no effect on OUT.
After the Control Word and initial count are written to a
Counter, the initial count will be loaded on the next CLK
pulse. This CLK pulse does not decrement the count, so for
an initial count of N, OUT does not go high until N + 1 CLK
pulses after the initial count is written.
CS
0
0
0
0
0
0
0
0
1
0
FIGURE 8. READ/WRITE OPERATIONS SUMMARY
RD
1
1
1
1
0
0
0
0
X
1
WR
X
0
0
0
0
1
1
1
1
1
A1
X
X
0
0
1
1
0
0
1
1
A0
X
X
0
1
0
1
0
1
0
1
Write into Counter 0
Write into Counter 1
Write into Counter 2
Write Control Word
Read from Counter 0
Read from Counter 1
Read from Counter 2
No-Operation (Three-State)
No-Operation (Three-State)
No-Operation (Three-State)
82C54
9
If a new count is written to the Counter it will be loaded on
the next CLK pulse and counting will continue from the new
count. If a two-byte count is written, the following happens:
(1) Writing the first byte disables counting. Out is set low
(2) Writing the second byte allows the new count to be
This allows the counting sequence to be synchronized by
software. Again OUT does not go high until N + 1 CLK
pulses after the new count of N is written.
If an initial count is written while GATE = 0, it will still be
loaded on the next CLK pulse. When GATE goes high, OUT
will go high N CLK pulses later; no CLK pulse is needed to
load the counter as this has already been done.
NOTES: The following conventions apply to all mode timing diagrams.
GATE
GATE
1. Counters are programmed for binary (not BCD) counting and for
2. The counter is always selected (CS always low).
3. CW stands for “Control Word”; CW = 10 means a control word of
4. LSB stands for Least significant “byte” of count.
5. Numbers below diagrams are count values. The lower number is
6. N stands for an undefined count.
7. Vertical lines show transitions between count values.
GATE
OUT
OUT
CLK
CLK
OUT
CLK
WR
WR
WR
immediately (no clock pulse required).
loaded on the next CLK pulse.
reading/writing least significant byte (LSB) only.
10, Hex is written to the counter.
the least significant byte. The upper number is the most signifi-
cant byte. Since the counter is programmed to read/write LSB
only, the most significant byte cannot be read.
CW = 10
CW = 10
CW = 10
N
N
N
N
N
N
LSB = 4
LSB = 3
LSB = 3
N
N
N
FIGURE 9. MODE 0
N
N
N
0
4
0
3
0
3
LSB = 2
0
3
0
2
0
2
0
1
0
2
0
2
0
1
0
2
0
2
0
1
0
0
0
1
FF
FF
0
0
0
0
FF
FE
FF
FF
FF
FF