IDT77V1253L25PGI IDT, Integrated Device Technology Inc, IDT77V1253L25PGI Datasheet - Page 14

• Manufacturer Part Number: IDT77V1253L25PGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1253L25PGI

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 3
• Type Of Atm Phy Interface: DPI/UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
ATM CELL FORMAT
Receiver Description
in reverse. The data is NRZI decoded before each symbol is reassembled.
The symbols are then sent to the 5b/4b decoder, followed by the Command
Byte Interpreter, De-Scrambler, and finally through a FIFO to the UTOPIA
or DPI interface to an ATM Layer device.
it does not attempt to correct them.
FUNCTIONAL BLOCK DIAGRAM (CONTINUED):
Note that although the IDT77V1253 can detect symbol and HEC errors,
The receiver side of the TC sublayer operates like the transmitter, but
Rx +
Rx
UDF = User Defined Field (or HEC)
Bit 7
Payload Byte 48
Payload Byte 1
Header Byte 1
Header Byte 2
Header Byte 3
Header Byte 4
Decoding
NRZI
Synthesizer
32.0MHz
UDF
OSC
& PLL
Clock
•
•
•
Bit 0
4781 drw 52
5
Figure 5. TC Receive Block Diagram
Decoding
5b/4b
PHY-ATM
Interface
Control -
RECV
14
synchronized. When not symbol-synchronized, the receiver will indicate a
significant number of bad symbols, and will deassert the Good Signal Bit as
described below. Synchronization is established immediately once that port
receives an Escape symbol, usually as part of the start-of-cell command byte
preceding the first received cell.
line is deemed 'bad'. The Interrupt Status Registers (registers 0x01, 0x11 and
0x21) contain a Good Signal Bit (bit 6, set to 0 = Bad signal initially) which shows
the status of the line per the following algorithm:
To declare 'Good Signal' (from "Bad" to "Good"):
3 Cells
Upon reset or the re-connect, each port's receiver is typically not symbol-
There is an up-down counter that counts from 7 to 0 and is initially set to
7. When the clock ticks for 1,024 cycles (32MHz clock, 1,024 cycles =
204.8 symbols) and no "bad symbol" has been received, the counter
decreases by one. However, if at least one "bad symbol" is detected
during these 1,024 clocks, the counter is increased by one, to a
maximum of 7. The Good Signal Bit is set to 1 when this counter reaches
0. The Good Signal Bit could be set to 1 as quickly as 1,433 symbols
(204.8 x 7) if no bad symbols have been received.
The IDT77V1253 monitors line conditions and can provide an interrupt if the
Start of Cell
4
4
RxRef
Command
Detection,
& Decode
Removal,
Byte
UTOPIA
or
DPI Interface
Reset
4
4
Scramble
Scrambler
Nibble
PRNG
De-
4781 drw 06
IDT77V1253
Next