IDT77V1253L25PGI IDT, Integrated Device Technology Inc, IDT77V1253L25PGI Datasheet - Page 32

• Manufacturer Part Number: IDT77V1253L25PGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1253L25PGI

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 3
• Type Of Atm Phy Interface: DPI/UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
DIAGNOSTIC CONTROL REGISTERS
INTERRUPT STATUS REGISTERS
Addresses: 0x02, 0x12, 0x22
Addresses: 0x01, 0x11, 0x21
Bit
1,0
Bit
7
6
5
4
3
2
7
6
5
4
3
2
0
1
sticky
sticky
sticky
sticky
sticky
sticky
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
0 = Bad Signal
0 = UTOPIA
00 = normal
Initial State
Initial State
0 = normal
1 = tri-state
0 = normal
0 = normal
0 = normal
0
0
0
0
0
0
0
Reserved
Good Signal Bit
1 - Good Signal
0 - Bad Signal
HEC error cell received
"Short Cell" Received
Interrupt signal which flags received cells with fewer than 53 bytes. This condition is detected when receiving
Start-of-Cell command bytes with fewer than 53 bytes between them.
Transmit Parity Error
If Bit 4 of Register 0x00 / 0x10 / 0x20 is set (Transmit Data Parity Check), this interrupt flags a transmit data
parity error condition. Odd parity is used.
Receive Signal Condition change
changes either from 'bad to good' or from 'good to bad'.
Received Symbol Error
Receive FIFO Overflow
accept additional data.
Force TxCLAV deassert (applicable only in Utop ia 1 and 2 modes)
Used during line loopback mode to prevent upstream system from continuing to send data to the
77V1253. Not applicable in DPI mode.
RxCLAV Operation Select (for Utopia 1 mode)
The UTOPIA standard dictates that during cell mode operation, if the receive FIFO no longer has a complete
cell available for transfer from PHY, RxCLAV is deasserted following transfer of the last byte out of the PHY
to the upstream system. With this bit set, early deassertion of this signal will o ccur coincident with the end of
Payload byte 44 (as in octet mode for TxCLAV). This provides early indication to the upstream system of this
impending condition.
Single/Multi-PHY configuration select (applicable and writable only in Utopia 1 mode)
0 = single:
1 = Multi-PHY mode: Tri-state RxDATA, RxPARITY and RxSOC when RxEN = 1
RFLUSH = Clear Receive FIFO
This signal is used to tell the TC to flush (clear) all data in the re ceive FIFO. The TC signals this completion
by clearing this bit.
Insert Transmit Payload Error
Tells TC to insert cell payload errors in transmitted cells. This can be used to test error detection and
recovery systems at destination station, or, under loopback control, at the local receiving station. This
payload error is accomplished by flipping bit 0 of the last cell payload byte.
Insert Transmit HEC Error
Tells TC to insert HEC error in Byte 5 of cell. This can be used to test error detection and recovery
systems in downstream switches, or, under loopback control, the local receiving station. The HEC error is
accomplished by flipping bit 0 of the HEC byte.
Loopback Control
bit # 1
0
1
1
0 = "Standard UTOPIA RxCLAV'
1 = "Cell mode = Byte mode"
0
0
1
0
Normal mode (receive from network)
PHY Loopback
Line Loopback
Never tri-state RxDATA, RxPARITY and RxSOC
See definitions on pages 14 and 15
Interrupt which indicates when the receive FIFO has filled and cannot
32
Set when a HEC erro r is detected on received cell.
Set when an undefined 5-bit symbol is received.
This interrupt is set when the received 'signal'
Function
Function
4781 tbl 16
IDT77V1253
4781 tbl 17