IDT77V1253L25PGI IDT, Integrated Device Technology Inc, IDT77V1253L25PGI Datasheet - Page 40

• Manufacturer Part Number: IDT77V1253L25PGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1253L25PGI

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 3
• Type Of Atm Phy Interface: DPI/UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
UTILITY BUS READ CYCLE
Trdpw
Name
Tcsrd
Tapw
Trdd
Ttria
Ttrid
Tdh
Tas
Tah
Tch
Trd
Tar
(output)
AD[7:0]
AD[7:0]
AD[7:0]
(input)
ALE
ALE
WR
RD
CS
CS
Min
____
____
10
10
20
0
5
0
0
5
5
0
Max
____
____
____
____
____
____
____
____
____
10
18
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip select to read enable
Min. RD pulse width
Data Valid hold time
Read Data access
Start of read to Data low-Z
Address setup to ALE
Address hold to ALE
ALE min pulse width
Address tri-state to RD assert
RD deassert to CS deassert
RD deassert to data tri-state
ALE low to start of read
Address
Tas
Tapw
Tas
Tapw
Address
Description
Figure 42. Utility Bus Read Cycle
Figure 43. Utility Bus Write Cycle
Tah
Tcswr
Tah
4781 tbl 34
Tcsrd
Tar
40
UTILITY BUS WRITE CYCLE
Taw
Tacswr
Twrpw
Trdd
Name
Tapw
Tdws
Tdwh
Taw
Tas
Tah
Tch
Twrpw
Tdws
Data (input)
Min
10
10
20
20
10
20
5
0
0
Trdpw
Trd
Max
____
____
____
____
____
____
____
____
____
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Tdwh
Data
Min. WR pulse width
ALE min pulse width
Address set up to ALE
Address hold time to ALE
CS Assert to WR
Write Data set up
Write Data hold time
WR deassert to CS deassert
ALE low to end of write
Tch
Tch
4781 drw 44
Ttrid
Description
Tdh
4781 drw 43
IDT77V1253
4781 tbl 35