UJA1061TW,512 NXP Semiconductors, UJA1061TW,512 Datasheet - Page 16
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UJA1061TW,512
Manufacturer Part Number
UJA1061TW,512
Description
Manufacturer
NXP Semiconductors
Datasheet
1.UJA1061TW512.pdf
(77 pages)
Specifications of UJA1061TW,512
Number Of Transceivers
1
Power Down Mode
Sleep/Standby
Operating Supply Voltage (min)
5.5V
Operating Temperature (max)
125C
Operating Temperature (min)
-40C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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NXP Semiconductors
UJA1061_6
Product data sheet
The behavior of pin RSTN is illustrated in
setting of the RLC bit (defines the reset length). Once an external reset event is detected
the system controller enters the Start-up mode. The watchdog now starts to monitor pin
RSTN as illustrated in
mode is entered as shown in
Fig 6.
Fig 7.
V
RSTN
V1
Reset pin behavior
Reset timing diagram
power-up
V
V
RSTN
RSTN
All information provided in this document is subject to legal disclaimers.
t
RSTNL
Figure
forced LOW
Rev. 06 — 9 March 2010
externally
RSTN
voltage
under-
RSTN externally forced LOW
Figure
7. If the RSTN pin is not released in time then Fail-safe
t
RSTNL
t
t
RSTNL
RSTNL
Fault-tolerant CAN/LIN fail-safe system basis chip
3.
watchdog
missing
access
t
Figure
RSTNL
6. The duration of t
voltage
under-
spike
t
WD(init)
t
WD(init)
001aad181
RSTNL
time
time
UJA1061
power-
© NXP B.V. 2010. All rights reserved.
down
V
V
rel(UV)(V1)
det(UV)(V1)
depends on the
coa054
time
time
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