82V2048DA IDT, Integrated Device Technology Inc, 82V2048DA Datasheet - Page 19

• Manufacturer Part Number: 82V2048DA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2048DA

• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Table-9 Built-in Waveform Template Selection
1.
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
2.5.2
pin TDNn/BPVIn is used as BPVI input. A low-to-high transition on this
pin inserts a bipolar violation on the next available mark in the transmit
data stream. Sampling occurs on the falling edges of TCLK. But in TAOS
(Transmit All Ones) with Analog Loopback, Remote Loopback and
Inband Loopback, the BPVI is disabled. In TAOS with Digital Loopback,
the BPVI is looped back to the system side, so the data to be transmitted
on TTIPn and TRINGn are all ones with no bipolar violation.
2.6
in receive path or not used. The selection is accomplished by setting pin
JAS in hardware mode or configuring bits JACF[1:0] in register GCF in
host mode, which affects all eight channels.
needed to be extracted for the internal synchronization, the jitter attenu-
ator is set in the receive path. Another use of the jitter attenuator is to
provide clock smoothing in the transmit path for applications such as
synchronous/asynchronous demultiplexing applications. In these appli-
cations, TCLK will have an instantaneous frequency that is higher than
the nominal T1/E1 data rate and in order to set the average long-term
TCLK frequency within the transmit line rate specifications, periods of
TCLK are suppressed (gapped).
Maximum cable loss at 772 kHz.
When configured in Single Rail Mode 2 with AMI line code enabled,
The jitter attenuator can be selected to work either in transmit path or
For applications which require line synchronization, the line clock
TS2
0
0
0
0
1
1
1
1
-0.2
-0.4
-0.6
1.2
0.8
0.6
0.4
0.2
BIPOLAR VIOLATION INSERTION
1
0
JITTER ATTENUATOR
0
Figure-12 DSX-1 Waveform Template
TS1
0
0
1
1
0
0
1
1
250
TS0
0
1
0
1
0
1
0
1
500
Time (ns)
Service
E1
T1
750
1000
Clock Rate
2.048 MHz
1.544 MHz
1250
19
120 Ω/75 Ω Cable
133-266 ft. ABAM
266-399 ft. ABAM
399-533 ft. ABAM
533-655 ft. ABAM
Table-10 Gap Width Limitation
gapped TCLK. In host mode, the FIFO length can be 32 X 2 or 64 X 2
bits by programming bit JADP in GCF. In hardware mode, it is fixed to 64
X 2 bits. The FIFO length determines the maximum permissible gap
width (see
cause FIFO overflow or underflow. The data is 16 or 32 bits’ delay
through the jitter attenuator in the corresponding transmit or receive
path. The constant delay feature is crucial for the applications requiring
“hitless” switching.
corner frequency (fc) for both T1 and E1. In hardware mode, the fc is
fixed to 2.5 Hz for T1 or 1.7 Hz for E1. Generally, the lower the fc is, the
higher the attenuation. However, lower fc comes at the expense of
increased acquisition time. Therefore, the optimum fc is to optimize both
the attenuation and the acquisition time. In addition, the longer FIFO
length results in an increased throughput delay and also influences the 3
dB corner frequency. Generally, it’s recommended to use the lower
corner frequency and the shortest FIFO length that can still meet jitter
attenuation requirements.
0-133 ft. ABAM
Cable Length
The jitter attenuator integrates a FIFO which can accommodate a
In host mode, bit JABW in GCF determines the jitter attenuator 3 dB
0.00
-0.20
Reserved
0.80
1.00
0.60
0.40
0.20
1.20
FIFO Length
Table-10 Gap Width
Figure-13 CEPT Waveform Template
-300
64 bit
32 bit
-200
INDUSTRIAL TEMPERATURE RANGES
-100
Limitation). Exceeding these values will
Time (ns)
Maximum Cable Loss (dB)
0
100
Max. Gap Width
0.6
1.2
1.8
2.4
3.0
-
-
200
56 UI
28 UI
300
(1)