82V2048DA IDT, Integrated Device Technology Inc, 82V2048DA Datasheet - Page 40

• Manufacturer Part Number: 82V2048DA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2048DA

• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
4
ACCESS PORT
as described in the IEEE 1149.1 standards.
registers plus a Test Access Port (TAP) controller. Control of the TAP is
achieved through signals applied to the TMS and TCK pins. Data is
shifted into the registers via the TDI pin, and shifted out of the registers
via the TDO pin. JTAG test data are clocked at a rate determined by
JTAG test clock.
The IDT82V2048 supports the digital Boundary Scan Specification
The boundary scan architecture consists of data and instruction
IEEE STD 1149.1 JTAG TEST
TRST
TDI
TCK
TMS
parallel latched output
Digital output pins
(Test Access Port)
Controller
IDR (Device Identification Register)
TAP
BSR (Boundary Scan Register)
IR (Instruction Register)
BR (Bypass Register)
Figure-25 JTAG Architecture
Control<6:0>
Digital input pins
40
Register), IDR (Device Identification Register), BR (Bypass Register)
and IR (Instruction Register). These will be described in the following
pages. Refer to
4.1
ISTER (IR)
executed or the data register to be accessed or both.
Table-19 Instruction Register Description on page 41
codes and the instructions related.
The JTAG boundary scan registers includes BSR (Boundary Scan
The IR with instruction decode block is used to select the test to be
The instructions are shifted in LSB first to this 3-bit register. See
JTAG INSTRUCTIONS AND INSTRUCTION REG-
Figure-25
Select
High-Z Enable
MUX
INDUSTRIAL TEMPERATURE RANGES
for architecture.
for details of the
TDO