82V2048DA IDT, Integrated Device Technology Inc, 82V2048DA Datasheet - Page 21

• Manufacturer Part Number: 82V2048DA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2048DA

• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
2.9
connected with TTIPn and TRINGn, can detect short circuit failure
between TTIPn and TRINGn pins. Bit SCPB in register GCF decides
whether the output driver short circuit protection is enabled. When the
short circuit protection is enabled, the driver output current is limited to a
typical value: 180 mAp. Also, register DF, DFI and DFM will be available.
When DFMON will detect a short circuit, register DF will be set. With a
short circuit failure detected and short circuit protection enabled, register
DFI will be set and an interrupt will be generated on pin INT.
2.10 TRANSMIT LINE SIDE SHORT CIRCUIT FAILURE
with TTIPn and TRINGn pins and limit the output current. In this case,
the output current is a limited value which is always lower than the
typical line short circuit current 180 mAp, even if the transmit line side is
shorted.
2.11 LINE PROTECTION
the line driver and improve the design robustness. In receive side, the
series resistors of 1 k
surges coupled in the device. The series resistors do not affect the
receiver sensitivity, since the receiver impedance is as high as 120 k
typically.
2.12 HITLESS PROTECTION SWITCHING (HPS)
feature for T1/E1 redundancy applications. This feature reduces the cost
of redundancy protection by eliminating external relays. Details of HPS
are described in relative Application Note.
2.13 SOFTWARE RESET
reset cycle. This operation set all the registers to their default value.
2.14 POWER ON RESET
default values. The power-on reset takes at least 10
when the power supply exceeds 2/3 VDDA.
2.15 POWER DOWN
low for more than 64 MCLK cycles (if MCLK is available) or about 30
(if MCLK is not available). In host mode, each transmit channel will also
be powered down by setting bit TPDNn in register e-TPDN to ‘1’.
MCLK is clocked or high, setting bit RPDNn in register e-RPDN to ‘1’ will
configure the corresponding receiver to be powered down.
An internal power Driver Failure Monitor (DFMON), parallel
In E1 or T1 with 5 V VDDT, a pair of 9.5
Refer to
In transmit side, the Schottky diodes D1~D4 are required to protect
The IDT82V2048 transceivers include an output driver with high-Z
Writing register RS will cause software reset by initiating about 1
During power up, an internal reset signal sets all the registers to
Each transmit channel will be powered down by pulling pin TCLKn
All the receivers will be powered down when MCLK is low. When
POWER DRIVER FAILURE MONITOR
DETECTION
Table-12 External Components Values
Ω
are used to protect the receiver against current
Ω
serial resistors connect
for details.
µ
s, starting from
µ
µ
Ω
s
s
21
2.16 INTERFACE WITH 5 V LOGIC
The internal input pads are tolerant to 5 V output from TTL and CMOS
family devices.
2.17 LOOPBACK MODE
Digital Loopback, Analog Loopback, Remote Loopback, Dual Loopback
and Inband Loopback. In host mode, these functions are implemented
by programming the registers DLB, ALB, RLB and Inband Loopback
register group respectively. In hardware mode, only Analog Loopback
and Remote Loopback can be selected by pin LPn.
2.17.1 DIGITAL LOOPBACK
can be configured in Local Digital Loopback. In this configuration, the
data and clock to be transmitted, after passing the encoder, are looped
back to Jitter Attenuator (if enabled) and decoder in the receive path,
then output on RCLKn, RDn/RDPn and CVn/RDNn. The data to be
transmitted are still output on TTIPn and TRINGn while the data
received on RTIPn and RRINGn are ignored. The Loss Detector is still in
use.
monitored by the LOS Detector (See
tion
ones signal will be output on RDPn/RDNn. With ATAO enabled, all ones
signal will be also output on TTIPn/TRINGn. AIS insertion can be
enabled by setting AISE bit in register GCF and ATAO can be enabled
by setting register ATAO (default disabled).
2.17.2 ANALOG LOOPBACK
each channel of the device can be configured in Analog Loopback. In
this configuration, the data to be transmitted output from the line driver
are internally looped back to the slicer and peak detector in the receive
path and output on RCLKn, RDn/RDPn and CVn/RDNn. The data to be
transmitted are still output on TTIPn and TRINGn while the data
received on RTIPn and RRINGn are ignored. The LOS Detector (See
2.4.4 Loss of Signal (LOS) Detection
tors the internal looped back data. If a LOS condition on TDPn/TDNn is
expected during Analog Loopback, ATAO should be disabled (default).
Figure-16
directly to do the external analog loopback test. Line impedance loading
is required to conduct the external analog loopback test.
2.17.3 REMOTE LOOPBACK
channel of the device can be set in Remote Loopback. In this configura-
tion, the data and clock recovered by the clock and data recovery
circuits are looped to waveform shaper and output on TTIPn and
TRINGn. The jitter attenuator is also included in loopback when enabled
in the transmit or receive path. The received data and clock are still
output on RCLKn, RDn/RDPn and CVn/RDNn while the data to be trans-
mitted on TCLKn, TDn/TDPn and BPVIn/TDNn are ignored. The LOs
Detector is still in use.
The IDT82V2048 can interface directly with 5 V TTL family devices.
The device provides five different diagnostic loopback configurations:
By programming the bits of register DLB, each channel of the device
During Digital Loopback, the received signal on the receive line is still
By programming the bits of register ALB or pulling pin LPn high,
The TTIPn and RTIPn, TRINGn and RRINGn cannot be connected
By programming the bits of register RLB or pulling pin LPn low, each
for details). In case of a LOS condition and AIS insertion enabled, all
Figure-15
shows the process.
shows the process.
Figure-17
INDUSTRIAL TEMPERATURE RANGES
shows the process.
for details) is still in use and moni-
2.4.4 Loss of Signal (LOS) Detec-