DJLXT384LE.B1SE001 Intel, DJLXT384LE.B1SE001 Datasheet - Page 53

• Manufacturer Part Number: DJLXT384LE.B1SE001
• Manufacturer: Intel

Specifications of DJLXT384LE.B1SE001

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

6.4.2
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Figure 5. 50% AMI Encoding
Note: The TAOS generator uses MCLK as a timing reference. To ensure that the output frequency is
Note: The TAOS generator uses MCLK as a timing reference. To ensure that the output frequency is
If TCLK:
Zero suppression is available only in Unipolar Mode. The zero-suppression type is HDB3 (E1
environment) or B8ZS (T1 environment). The scheme selected depends on whether the device is
set for T1 or E1 operation (determined by LEN2-0 pulse shaping settings). The LXT384
Transceiver also supports AMI line coding/decoding as shown in
Each output driver is supplied by its own TVCC and TGND power-supply pins. The transmit pulse
shaper is bypassed if no MCLK is supplied. When in this condition, if TCLK is pulled High, then
TPOS and TNEG control the pulse width and polarity on TTIP and TRING. With MCLK supplied
and TCLK pulled High, the driver enters TAOS (Transmit All Ones pattern).
within specification limits, MCLK must have the applicable stability. TAOS is inhibited during
Remote Loopback.
Transmitter Pulse Shaping
Pulse shaping is a means of converting an input logic ‘1’ into a valid output mark so that the output
pulse can be changed (or ‘shaped’) to adhere to the ITU-T G.703 pulse template (shown in
31
The transmit pulse shaper is bypassed if no MCLK is supplied. In this case, if TCLK is pulled high
then TPOS and TNEG control the pulse width and polarity on TTIP and TRING. With MCLK
supplied and TCLK pulled High, the driver enters TAOS (Transmit All Ones pattern).
within specification limits, MCLK must have the applicable stability. TAOS is inhibited during
Remote Loopback.
•
•
•
•
TRING
TTIP
in
Is not supplied, the transmitter output remains powered down and the TTIP/TRING outputs
are held in a high-impedance tristate. Fast output tristatability is also available through the OE
pin (all ports) or the port’s OEx bit in the Output Enable Register (OER).
Is supplied, the input signals that the transmitter samples depends on the TNEG/UBS setting.
When TNEG/UBS is connected:
In Hardware mode, use the CODEN pin to select AMI coding/decoding.
In host mode, bit 4 in the GCR (Global Control Register) selects AMI coding/decoding.
— Low (bipolar I/O), the transmitter samples TPOS/TNEG input signals on the falling edge
— High for more than 16 consecutive TCLK cycles (unipolar I/O), the transmitter samples
Chapter 13.0, “Mask
of TCLK.
TDATA inputs on the falling edge of TCLK.
Bit Cell
1
Specifications”).
0
Intel
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
1
Figure
5.
Figure
53