WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 54

• Manufacturer Part Number: WJLXT385LE.B1
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT385LE.B1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

6.3.3
6.3.3.1
54
Intel
®
LXT385 Octal E1 S/H PCM Transceiver with JA
Receiver Loss-Of-Signal Detector
The LXT385 ransceiver loss-of-signal (LOS) detector circuit is designed to detect loss of signals in
both analog and digital domains. This circuit is independent of the data slicer.
The receiver monitor loads a digital counter at the RCLK frequency. The counter is incremented
each time a zero is received, and reset to zero each time a one (mark) is received. Depending on the
operation mode, a certain number of consecutive zeros sets the LOS signal. The recovered clock is
replaced by MCLK at the RCLK output with a minimum amount of phase errors. MCLK is
required for receive operation. When the LOS condition is cleared, the LOS flag is reset and
another transition replaces MCLK with the recovered clock at RCLK. RPOS/RNEG will reflect the
data content at the receiver input during the entire LOS detection period for that channel.
G.755 and ETSI 300 233 - Loss of Signal Detection
5. The data slicer processes the received signal, after which the signal simultaneously goes to
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both the clock and data-recovery sections.
In hardware mode, it complies with the latest ITU G.775 recommendations.
Under software control, the detector can be configured to comply to the ETSI ETS 300 233
specification (
In G.775 mode a loss of signal is detected if the signal is below 200mV (typical) for 32
consecutive pulse intervals. The LOS flag is reset when the received signal reaches 12.5%
ones density (4 marks in a sliding 32-bit period) with no more than 15 consecutive zeros and
the signal level exceeds 250mV (typical). Following the next MCLK transition, MCLK is
replaced with a recovered clock at the RCLK output.
In ETSI 300 233 mode, a loss of signal is detected if the signal is below 200mV for 2048
consecutive intervals (1 ms). The LOS condition is cleared and the output pin returns to Low
when the incoming signal has transitions when the signal level is equal or greater than 250mV
for more than 32 consecutive pulse intervals. This mode is activated by setting the LACS
register bit to one.
— The data and timing recovery circuits provide an input jitter tolerance better than required
— Depending on the options selected, recovered clock and data signals may be routed
by ITU G.823, as shown in Test
Jitter Tolerance Compared to ITU G.823” on page 128
through the jitter attenuator, through the HDB3/AMI decoder, and may be output to the
framer as either bipolar or unipolar data.
LACS
Register).
Specifications,Figure 32, “Intel® LXT385 Transceiver
.
Revision Date: 19-Jan-2006
Document Number: 249252
Revision Number: 006