WJLXT385LE.B1 Cortina Systems Inc, WJLXT385LE.B1 Datasheet - Page 65

• Manufacturer Part Number: WJLXT385LE.B1
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT385LE.B1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

6.6
Document Number: 249252
Revision Number: 006
Revision Date: 19-Jan-2006
Figure 7. Jitter Attenuator
RNEGi
RPOSi
TNEGi
TPOSi
RCLKi
TCLKi
MCLK
Jitter Attenuation
Figure 7
an external crystal nor a reference clock that has a frequency higher than the line frequency.
Data signals are clocked into the FIFO with the associated clock signal (TCLKi or RCLKi) and are
clocked out of the FIFO with the JA clock after removing jitter (TCLKo when TCLKi is used, or
RCLKo when RCLKi is used). When the FIFO is within two bits of overflowing or underflowing,
the FIFO adjusts the output clock by
constant throughput delay of either 16 bits (when a 32 x 2-bit register is used) or 32 bits (when a 64
x 2-bit register is used).
JASEL0-1
shows the internal LXT385 ransceiver jitter attenuation (JA) unit, which requires neither
x 32
IN CLK
IN
Clock Recovery Unit
1/8
FIFO
FIFO64
of a bit period. For the associated path, the JA produces a
Intel
®
LXT385 Octal E1 S/H PCM Transceiver with JA
OUT CLK
OUT
o = outputs
i = inputs
JASEL0-1
GCR control bits
TPOSo
RPOSo
TNEGo
RNEGo
TCLKo
RCLKo
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