USB2229-NU-02 Standard Microsystems (SMSC), USB2229-NU-02 Datasheet - Page 17

• Manufacturer Part Number: USB2229-NU-02
• Manufacturer: Standard Microsystems (SMSC)

Specifications of USB2229-NU-02

• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

5th Generation Hi-Speed USB Flash Media and IrDA Controller with Integrated Card Power FETs
Datasheet
SMSC USB2229/USB2230
Input/External Clock
Memory Data Bus
Memory Address
Memory Address
Memory Address
Crystal Output
Crystal
NAME
Input
Bus
Bus
Bus
SEL_CLKDRV
SYMBOL
MA[15:3]
TX_POL
MD[7:0]
XTAL1/
XTAL2
CLKIN
MA3/
MA2/
Table 6.1 USB2229/USB2230 Pin Descriptions
MEMORY/IO INTERFACE
BUFFER
OCLKx
I/O8PU
I/O8PD
ICLKx
TYPE
IO8
O8
DATASHEET
17
24Mhz Crystal or external 24/48 MHz clock input.
This pin can be connected to one terminal of the crystal
or can be connected to an external 24/48Mhz clock
when a crystal is not used.
Note:
24Mhz Crystal
This is the other terminal of the crystal, or left open
when an external clock source is used to drive
XTAL1/CLKIN. It may not be used to drive any external
circuitry other than the crystal circuit.
When ROMEN bit of GPIO_IN1 register = 0, these
signals are used to transfer data between the internal
CPU and the external program memory.
These pins have internally controlled weak pull-up
resistors.
These signals address memory locations within the
external memory.
MA3 Addresses memory locations within the external
memory.
During nRESET assertion, TX_POL will select the
operating polarity of the IR LED (active high or active
low) and the weak pull-up resistor will be enabled.
When nRESET is negated, the value on this pin will be
internally latched and this pin will revert to MA3
functionality, the internal pull-up will be disabled.
MA2 Addresses memory locations within the external
memory.
SEL_CLKDRV. During nRESET assertion, this pins will
select the operating clock mode (crystal or externally
driven clock source), and a weak pull-down resistor is
enabled. When nRESET is negated, the value will be
internally latched and this pin will revert to MA2
functionality, the internal pull-down will be disabled.
‘0’ = Crystal operation (24MHz only)
‘1’ = Externally driven clock source (24MHz or 48MHz)
Note:
1. IDLE bit (PCON.0) is 1.
2. INT2 is negated
3. SLEEP bit of CLOCK_SEL is 1.
If the latched value is ‘0’, then the MA2 pin will function
identically to the MA[15:3] pins at all times (other than
during nRESET assertion).
The ‘MA[2:0] pins will be sampled while
nRESET is asserted, and the value will be
latched upon nRESET negation. This will
determine the clock source and value.
If the latched value is ‘1’, then the MA2 pin is
tri-stated when the following conditions are
true:
DESCRIPTION
Revision 1.4 (09-14-07)