USB2601-NU-02 Standard Microsystems (SMSC), USB2601-NU-02 Datasheet - Page 19

• Manufacturer Part Number: USB2601-NU-02
• Manufacturer: Standard Microsystems (SMSC)

Specifications of USB2601-NU-02

• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: TQFP
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

4th Generation USB 2.0 Flash Media Controller with Integrated Card Power FETs & HS Hub
Datasheet
SMSC USB2601/USB2602
Input/External Clock
Select Clock Drive
General Purpose
General Purpose
USB Transceiver
1.8V PLL Power
3.3V PLL Power
Crystal Output
RESET input
Clock Select
Card Power
Analog Test
TEST Input
Crystal
NAME
Input
Bias
I/O
I/O
Or
SEL_CLKDRV
CLK_SEL[1:0]
CRD_PWR2
GPIO[15:12]
VDD18PLL
VDD33PLL
RESET_N
SYMBOL
GPIO11/
XTAL1/
ATEST
RBIAS
XTAL2
CLKIN
TEST
BUFFER
OCLKx
I/O8PD
I/O8PD
ICLKx
TYPE
I/O8
I/O8
AIO
IPD
ANALOG POWER
IS
DATASHEET
I
19
GPIO: These pins may be used either as input, edge
sensitive interrupt input, or output.
CRD_PWR: Card Power drive of 3.3V @ 200mA.
These pins may be used either as input, or output.
This active low signal is used by the system to reset the
chip. The active low pulse should be at least 1μs wide.
Used for testing the IC. User must treat either as a no-
connect, or connect to the ground.
A 12.0kΩ, ± 1.0% resistor is attached from VSS to this
pin, in order to set the transceiver’s internal bias
currents.
This signal is used for testing the analog section of the
chip and should be connected to VDDA33 for normal
operation.
24MHz Crystal or external clock input.
This pin can be connected to one terminal of the crystal
or can be connected to an external 24MHz clock when
a crystal is not used.
Note:
24MHz Crystal
This is the other terminal of the crystal, or left open
when an external clock source is used to drive
XTAL1/CLKIN. It may not be used to drive any external
circuitry other than the crystal circuit.
SEL_CLKDRV. During RESET_N assertion, this pin will
select the operating clock mode (crystal or externally
driven clock source), and a weak pull-down resistor is
enabled. When RESET_N is negated, the value will be
internally latched and the internal pull-down will be
disabled.
‘0’ = Crystal operation (24MHz)
‘1’ = Externally driven clock source (24MHz)
SEL[1:0]. During RESET_N assertion, these pins will
select the operating frequency of the external clock, and
the corresponding weak pull-down resistors are
enabled. When RESET_N is negated, the value on
these pins will be internal latched and the internal pull-
downs will be disabled.
SEL[1:0] = ‘00’. 24MHz
SEL[1:0] = ‘01’. RESERVED
SEL[1:0] = ‘10’. RESERVED
SEL[1:0] = ‘11’. RESERVED
1.8V Output from the internal 1.8V PLL regulator
3.3V Input to the internal 1.8V PLL regulator.
The ‘SEL_CLKDRV and CLK_SEL[1:0]’ pins
will be sampled while RESET_N is asserted,
and the value will be latched upon RESET_N
negation. This will determine the clock source
and value.
DESCRIPTION
Revision 1.6 (06-20-08)