LAN9215-MT Standard Microsystems (SMSC), LAN9215-MT Datasheet - Page 34

• Manufacturer Part Number: LAN9215-MT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9215-MT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

Revision 2.7 (03-15-10)
3.7
3.8
3.8.1
Default Mode - Word Swap Register equal to 0x00000000 or any value other than 0xFFFFFFFF
Word Swap Mode - Word Swap Register equal to 0xFFFFFFFF
ADDRESS
A1 PIN
The General Purpose Timer is a programmable block that can be used to generate periodic host
interrupts. The resolution of this timer is 100uS.
The GP Timer loads the GPT_CNT Register with the value in the GPT_LOAD field and begins counting
down when the TIMER_EN bit is set to a ‘1.’ On a reset, or when the TIMER_EN bit changes from
set ‘1’ to cleared ‘0,’ the GPT_LOAD field is initialized to FFFFh. The GPT_CNT register is also
initialized to FFFFh on a reset. Software can write the pre-load value into the GPT_LOAD field at any
time; e.g., before or after the TIMER_EN bit is asserted. The GPT Enable bit TIMER_EN is located in
the GPT_CFG register.
Once enabled, the GPT counts down either until it reaches 0000h or until a new pre-load value is
written to the GPT_LOAD field. At 0000h, the counter wraps around to FFFFh, asserts the GPT
interrupt status bit and the IRQ signal if the GPT_INT_EN bit is set, and continues counting. The GPT
interrupt status bit is in the INT_STS Register. The GPT_INT hardware interrupt can only be set if the
GPT_INT_EN bit is set. GPT_INT is a sticky bit (R/WC); i.e., once the GPT_INT bit is set, it can only
be cleared by writing a ‘1’ to the bit.
The LAN9215 can optionally load its MAC address from an external serial EEPROM. If a properly
configured EEPROM is detected by the LAN9215 at power-up, hard reset or soft reset, the ADDRH
and ADDRL registers will be loaded with the contents of the EEPROM. If a properly configured
EEPROM is not detected, it is the responsibility of the host LAN Driver to set the IEEE addresses.
The LAN9215 EEPROM controller also allows the host system to read, write and erase the contents
of the Serial EEPROM. The EEPROM controller supports most “93C46” type EEPROMs configured for
128 x 8-bit operation.
MAC Address Auto-Load
On power-up, hard reset or soft reset, the EEPROM controller attempts to read the first byte of data
from the EEPROM (address 00h). If the value A5h is read from the first address, then the EEPROM
General Purpose Timer (GP Timer)
EEPROM Interface
A1 = 0
A1 = 1
A1 = 0
A1 = 1
Table 3.7 Word Swap Control(16-bit mode only)
D[15:8]
Byte 1
Byte 3
Byte 3
Byte 1
BYTE ORDER
DATASHEET
Byte 0
Byte 2
Byte 2
Byte 0
D[7:0]
34
When A1=0, the data bus is mapped to the low
When A1=0, the data bus is mapped to the high
order words of CSRs and FIFOs. When A1=1, the
data bus is mapped to the high-order words of
CSRs and FIFOs. Since low-order words are
always transmitted/received first, A1=0 data will
always precede A1=1 data.
order words of CSRs and FIFOs. When A1=1, the
data bus is mapped to the low order words of CSRs
and FIFOs. In this case A1=1 data will always
precede A1=0 data.
16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support
DESCRIPTION
SMSC LAN9215
Datasheet