LAN9514-JZX Standard Microsystems (SMSC), LAN9514-JZX Datasheet - Page 6

• Manufacturer Part Number: LAN9514-JZX
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9514-JZX

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

Chapter 1 Introduction
Revision 1.0 (11-24-09)
1.1
1.1.1
DP/DM
USB
JTAG
LAN9514/LAN9514i
Block Diagram
Overview
The LAN9514/LAN9514i is a high performance Hi-Speed USB 2.0 hub with a 10/100 Ethernet
controller. With applications ranging from embedded systems, desktop PCs, notebook PCs, printers,
game consoles, and docking stations, the LAN9514/LAN9514i is targeted as a high performance, low
cost USB/Ethernet and USB/USB connectivity solution.
The LAN9514/LAN9514i contains an integrated USB 2.0 hub, four integrated downstream USB 2.0
PHYs, an integrated upstream USB 2.0 PHY, a 10/100 Ethernet PHY, a 10/100 Ethernet Controller, a
TAP controller, and a EEPROM controller. A block diagram of the LAN9514/LAN9514i is provided in
Figure
The LAN9514/LAN9514i hub provides over 30 programmable features, including:
PortMap (also referred to as port remap) which provides flexible port mapping and disabling
sequences. The downstream ports of the LAN9514/LAN9514i hub can be reordered or disabled in any
sequence to support multiple platform designs’ with minimum effort. For any port that is disabled, the
LAN9514/LAN9514i automatically reorders the remaining ports to match the USB host controller’s port
numbering scheme.
PortSwap which adds per-port programmability to USB differential-pair pin locations. PortSwap allows
direct alignment of USB signals (D+/D-) to connectors avoiding uneven trace length or crossing of the
USB differential signals on the PCB.
PHYBoost which enables four programmable levels of USB signal drive strength in USB port
transceivers. PHYBoost attempts to restore USB signal integrity that has been compromised by system
level variables such as poor PCB layout, long cables, etc..
Downstream
Controller
Upstream
USB PHY
USB PHY
TAP
1.1.
DP/DM
USB
Downstream
Figure 1.1 Internal Block Diagram
USB PHY
USB 2.0
Hub
DP/DM
USB
DATASHEET
6
Downstream
Controller
USB PHY
Ethernet
10/100
DP/DM
USB
USB 2.0 Hub and 10/100 Ethernet Controller
Downstream
Controller
USB PHY
EEPROM
Ethernet
PHY
SMSC LAN9514/LAN9514i
DP/DM
USB
Datasheet
EEPROM
Ethernet