GD82551ER Intel, GD82551ER Datasheet - Page 32

• Manufacturer Part Number: GD82551ER
• Manufacturer: Intel

Specifications of GD82551ER

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Not Compliant

82551ER — Networking Silicon
5.2.2
24
If any one of the above conditions is not true, the 82551ER uses the MW command. If an MWI
cycle has started and one of the conditions is no longer valid (for example, the data space in the
memory buffer is now less than CLS), then the 82551ER terminates the MWI cycle at the end of
the cache line. The next cycle is either an MW or MWI cycle depending on the conditions listed
above.
If the 82551ER started a MW cycle and reached a cache line boundary, it either continues or
terminates the cycle depending on the Terminate Write on Cache Line configuration bit of the
82551ER Configure command (byte 3, bit 3). If this bit is set, the 82551ER terminates the MW
cycle and attempts to start a new cycle. The new cycle is an MWI cycle if this bit is set and all of
the above conditions are met. If the bit is not set, the 82551ER continues the MW cycle across the
cache line boundary if required.
5.2.1.2.2 Read Align
The Read Align feature enhances the 82551ER’s performance in cache line oriented systems. In
these particular systems, starting a PCI transaction on a non-cache line aligned address may cause
low performance.
To resolve this performance anomaly, the 82551ER attempts to terminate transmit DMA cycles on
a cache line boundary and start the next transaction on a cache line aligned address. This feature is
enabled when the Read Align Enable bit is set in the 82551ER Configure command (byte 3, bit 2).
If this bit is set, the 82551ER operates as follows:
This feature is not recommended for use in non-cache line oriented systems since it may cause
shorter bursts and lower performance. If this feature is used, it is recommended that the CLS
register in PCI Configuration space is set to 8 or 16.
5.2.1.2.3 Error Handling
Data Parity Errors: As an initiator, the 82551ER checks and detects data parity errors that occur
during a transaction. If the Parity Error Response bit is set (PCI Configuration Command register,
bit 6), the 82551ER also asserts PERR# and sets the Data Parity Detected bit (PCI Configuration
Status register, bit 8). In addition, if the error was detected by the 82551ER during read cycles, it
sets the Detected Parity Error bit (PCI Configuration Status register, bit 15).
Clock Run Signal
This signal is active in PCI bus operating modes. The Clock Run signal is an open drain I/O signal.
It is used as a bi-directional channel between the host and the devices.
6. The MWI Enable bit in the 82551ER Configure command must be set to 1b.
•
•
•
When the 82551ER is almost out of resources on the transmit DMA (that is, the transmit FIFO
is almost full), it attempts to terminate the read transaction on the nearest cache line boundary.
When the arbitration counter’s feature is enabled (in other words, the Transmit DMA
Maximum Byte Count value is set in the Configure command), the 82551ER switches to other
pending DMAs on cache line boundary only.
The host de-asserts the CLK_RUN# signal to indicate that the clock is about to be stopped or
slowed down to a non-operational frequency.
Datasheet