GD82551ER Intel, GD82551ER Datasheet - Page 33

• Manufacturer Part Number: GD82551ER
• Manufacturer: Intel

Specifications of GD82551ER

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Not Compliant

5.2.3
5.3
5.3.1
5.3.1.1
Datasheet
Proper operation requires that the system latency from the nominal PCI CLK to CLK_RUN#
assertion should be less than 0.5 µs. If the system latency is longer than 0.5 µs, there is an increase
in receive overruns. In these types of systems, the Clock Run functionality should be disabled. In
this case, the 82551ER will claim the PCI clock even during idle time. If the CLK_RUN# signal is
not used, it must be connected to a pull-down resistor.
Power Management Event
The 82551ER supports power management indications in the PCI mode. The PME# output pin
provides an indication of a power management event in PCI systems.
PCI Power Management
The 82551ER supports interesting packet wake-up and the capability to wake the system on a link
status change from a low power state. The 82551ER enables the host system to be in a sleep state
and remain virtually connected to the network. After a power management event or link status
change is detected, the 82551ER will wake the host system. The sections below describe these
events, the 82551ER power states, and estimated power consumption at each power state.
Power States
The 82551ER has one set of PCI power management registers and implements all four power states
as defined in the Power Management Network Device Class Reference Specification, Revision 1.0.
The four device power states, D0 through D3, vary from maximum power consumption at D0 to
the minimum power consumption at D3.
PCI transactions are only allowed in the D0 state, except for host accesses to the 82551ER’s PCI
configuration registers. The D1 and D2 power management states enable intermediate power
savings while providing the system wake-up capabilities. In the D3 cold state, the 82551ER can
provide wake-up capabilities only if auxiliary power is supplied. Wake-up indications from the
82551ER are provided by the Power Management Event (PME#) signal in PCI implementations.
D0 Power State
As defined in the Network Device Class Reference Specification, the device is fully functional in
the D0 power state. In this state, the 82551ER receives full power and should be providing full
functionality. In the 82551ER the D0 state is partitioned into two substates, D0 Uninitialized (D0u)
and D0 Active (D0a).
D0u is the 82551ER’s initial power state following a Power-on Reset (POR) event and before the
Base Address Registers (BARs) are accessed. Initialization of the CSR, Memory, or I/O Base
Address Registers in the PCI Configuration space switches the 82551ER from the D0u state to the
D0a state.
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The host asserts the CLK_RUN# signal when the clock is either running at a normal operating
frequency or about to be started.
The 82551ER asserts the CLK_RUN# signal to indicate that the PCI clock must prevent the
host from stopping or to request that the host restore the clock if it was previously stopped.
Networking Silicon — 82551ER
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