GD82551ER Intel, GD82551ER Datasheet - Page 65

• Manufacturer Part Number: GD82551ER
• Manufacturer: Intel

Specifications of GD82551ER

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Not Compliant

8.2
Datasheet
Table 23. Statistical Counters
Statistical Counters
The 82551ER provides information for network management statistics by providing on-chip
statistical counters that count a variety of events associated with both transmit and receive. The
counters are updated by the 82551ER when it completes the processing of a frame (that is, when it
has completed transmitting a frame on the link or when it has completed receiving a frame). The
Statistical Counters are reported to the software on demand by issuing the Dump Statistical
Counters command or Dump and Reset Statistical Counters command in the SCB Command Unit
Command (CUC) field.
12
16
20
24
28
32
36
40
ID
0
4
8
Transmit Good Frames
Transmit Maximum Collisions
(MAXCOL) Errors
Transmit Late Collisions
(LATECOL) Errors
Transmit Underrun Errors
Transmit Lost Carrier Sense (CRS)
Transmit Deferred
Transmit Single Collisions
Transmit Multiple Collisions
Transmit Total Collisions
Receive Good Frames
Receive CRC Errors
Counter
This counter contains the number of frames that were
transmitted properly on the link. It is updated only after the
actual transmission on the link is completed, not when the
frame was read from memory, as is done for the Transmit
Command Block status.
This counter contains the number of frames that were not
transmitted because they encountered the configured
maximum number of collisions.
This counter contains the number of frames that were not
transmitted due to an encountered collision after the
configured slot time.
A transmit underrun occurs because the system bus cannot
keep up with the transmission. This counter contains the
number of frames that were either not transmitted or
retransmitted due to a transmit DMA underrun. If the 82551ER
is configured to retransmit on underrun, this counter may be
updated multiple times for a single frame.
This counter contains the number of frames that were
transmitted by the 82551ER despite the fact that it detected
the de-assertion of CRS during the transmission.
This counter contains the number of frames that were
deferred before transmission due to activity on the link.
This counter contains the number of transmitted frames that
encountered one collision.
This counter contains the number of transmitted frames that
encountered more than one collision.
This counter contains the total number of collisions that were
encountered while attempting to transmit. This count includes
late collisions and frames that encountered MAXCOL.
This counter contains the number of frames that were
received properly from the link. It is updated only after the
actual reception from the link is completed and all the data
bytes are stored in memory.
This counter contains the number of aligned frames discarded
because of a CRC error. This counter is updated, if needed,
regardless of the Receive Unit state. The Receive CRC Errors
counter is mutually exclusive of the Receive Alignment Errors
and Receive Short Frame Errors counters.
Networking Silicon — 82551ER
Description
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