LAN9215I-MT Standard Microsystems (SMSC), LAN9215I-MT Datasheet - Page 126
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LAN9215I-MT
Manufacturer Part Number
LAN9215I-MT
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9215I-MT.pdf
(139 pages)
Specifications of LAN9215I-MT
Operating Supply Voltage (typ)
3.3V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Lead Free Status / RoHS Status
Compliant
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Revision 2.7 (03-15-10)
6.6
SYMBOL
t
cycle
t
t
t
t
t
t
csh
asu
dsu
csl
ah
dh
nCS, nWR
Data Bus
A[7:1]
PIO writes are used for all LAN9215i write cycles. PIO writes can be performed using Chip Select
(nCS) or Write Enable (nWR). Either or both of these control signals must go high between cycles for
the period specified.
Note: The “Data Bus” width is 16 bits.
Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either
PIO Writes
DESCRIPTION
Write Cycle Time
nCS, nWR Deassertion Time (see Note below)
Address Setup to nCS, nWR Assertion
Address Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
nCS, nWR Assertion Time
or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.
Parameters t
csh
and t
Figure 6.5 PIO Write Cycle Timing
Table 6.7 PIO Write Cycle Timing
csl
must be extended using wait states to meet the t
DATASHEET
16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
126
MIN
165
32
13
0
7
0
0
TYP
133
cycle
MAX
minimum.
SMSC LAN9215i
Datasheet
UNITS
ns
ns
ns
ns
ns
ns
ns
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