AT84CS001VTP E2V, AT84CS001VTP Datasheet - Page 13

• Manufacturer Part Number: AT84CS001VTP
• Manufacturer: E2V

Specifications of AT84CS001VTP

• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 110C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.9
e2v semiconductors SAS 2009
Clock Input Delay Cell (CLKDACTRL)
Figure 3-12. Standalone Delay Cell Tuning Range vs. T
A fine tune delay cell is provided to fine-tune the delay between the clock path and the data path at the
DMUX input. This adjustment may be necessary depending on the sampling rate and/or if there are mis-
alignments or skews on the different input data. However, data path skews should be maintained below
50 ps.
For more information on CLKDACTRL values to be applied, depending on the sampling rate, please
refer to the application note Interfacing ADC with AT84CS001 DMUX, reference 0867.
The delay is controlled by the CLKDACTRL analog control input. It ranges from -275 to 275 ps for CLK-
DACTRL varying from V
the one used in standalone delay cell.
This embedded delay line has characteristics similar to those of the standalone delay cell described in
“Standalone Delay Cell (DAI, DAIN) (DAO, DAON)” above.
This delay depends on the center position of the (CLK, CLKN) clock path in relation to the digital input
data in the DMUX input data paths (I0, I0N) …(I9, I9N) and (IOR, IORN).
Figure 3-13. Block Diagram of the Clock Input Delay Cell
560
540
520
500
480
460
440
420
400
-40
-30
(CLK, CLKN)
CLKDACTRL
-20
CCD
/3 to (2 × V
-10
0
2
CCD
10
)/3. The transfer characteristics of the delay cell is identical to
20
(-275 to 275 ps)
Delay
30
Tj (C)
40
J
50
2
60
70
clock signal
Internal
80
0809E–BDC–05/09
AT84CS001
90
100
110
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