ADM6992CXABT1XP Lantiq, ADM6992CXABT1XP Datasheet
ADM6992CXABT1XP
Specifications of ADM6992CXABT1XP
Related parts for ADM6992CXABT1XP
ADM6992CXABT1XP Summary of contents
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Edition 2005-11-25 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2005. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of ...
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Two Port Bridge Fiber to Fast Ethernet Converter Revision History: 2005-11-25, Rev. 1.02 Previous Version: Page/Date Subjects (major changes since last revision) 2004-05-05 Rev. 1.0, First release of NINJA C (ADM6992C) 2005-05-20 Rev. 1.01, Document conversion from Word to FrameMaker ...
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Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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EEPROM Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 NINJA C/CX (ADM6992C/CX) Block Diagram 9 Figure 2 NINJA C/CX (ADM6992C/CX) 64-Pin Assignment 10 Figure 3 SMI Read Operation 25 Figure 4 SMI Write Operation 26 Figure 5 Power on Reset Timing 76 Figure 6 ...
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List of Tables Table 1 Data Lengths Conventions 9 Table 2 Abbreviations for Pin Type 11 Table 3 Abbreviations for Buffer Type 11 Table 4 Port 0/1 Twisted Pair Interface (8 Pins) 12 Table 5 LED Interface (12 Pins) 12 ...
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Product Overview Features and the block diagram. 1.1 Overview The NINJA C/CX (ADM6992C/CX single chip integrating two 10/100 Mbps MDIX TX/FX transceivers with a two-port 10/100M Ethernet L2 switch controller. Features include a converter mode to meet ...
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Block Diagram Figure 1 NINJA C/CX (ADM6992C/CX) Block Diagram 1.4 Data Lengths Conventions Table 1 Data Lengths Conventions qword 64 bits dword 32 bits word 16 bits byte 8 bits nibble 4 bits Data Sheet 9 Ninja C/CX ADM6992C/CX ...
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NINJA C/CX Interface Description This chapter describes Pin Diagram, Pin Type and Buffer Type Abbreviations, and Pin Descriptions. 2.1 Pin Diagram Figure 2 NINJA C/CX (ADM6992C/CX) 64-Pin Assignment Data Sheet NINJA C/CX Interface Description 10 Ninja C/CX ADM6992C/CX Rev. ...
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Pin Type and Buffer Type Abbreviations Standardized abbreviations: Table 2 Abbreviations for Pin Type Abbreviations Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I bidirectional input/output signal. AI Input. Analog levels. AO Output. ...
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Pin Descriptions Interfaces: • Port 0/1 Twisted Pair Interface, 8 pins • LED Interface, 12 pins • EEPROM Interface, 4 pins • Configuration Interface, 28 pins • Ground/Power Interface, 27 pins • Miscellaneous, 14 pins Note: If not specified, ...
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Table 5 LED Interface (12 Pins) (cont’d) Pin or Name Pin Ball Type No. 53 LNKACT_1 I/O LED_DATA_1 LEDMODE_1 61 DUPCOL_0 I/O LED_COL_0 DIS_LEARN 62 DUPCOL_1 I/O LED_COL_1 58 LDSPD_0 I/O FXMODE0 Data Sheet Buffer Function Type TTL, PORT1 Link ...
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Table 5 LED Interface (12 Pins) (cont’d) Pin or Name Pin Ball Type No. 60 LDSPD_1 I/O LED_FIBER_SD LEDMODE2 63 LED_LINK_0 I/O FXMODE1 64 LED_LINK_1 I/O BYPASS_PAUS E 55 LED_FULL_0 I/O CHIPID_0 Data Sheet Buffer Function Type TTL, Speed LED, ...
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Table 5 LED Interface (12 Pins) (cont’d) Pin or Name Pin Ball Type No. 56 LED_FULL_1 I/O CHIPID_1 50 LED_LPBK I/O CHIPID_2 51 LED_WAN_FAIL O DISBP Table 6 EEPROM Interface (4 Pins) Pin or Name Pin Ball Type No. 2 ...
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Table 6 EEPROM Interface (4 Pins) (cont’d) Pin or Name Pin Ball Type No. 4 EECK/SDC I/O 3 EEDI/SDIO I/O Table 7 Configuration Interface (28 Pins) Pin or Name Pin Ball Type No. 47 P0_ANDIS I 46 P0_RECHALF I 45 ...
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Table 7 Configuration Interface (28 Pins) (cont’d) Pin or Name Pin Ball Type No. 34 XOVEN I 35 P0_MDI I Table 8 Ground/Power Interface (27 Pins) Pin or Name Pin Ball Type No. 20, 28 GNDTR GND, A 17, 31 ...
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Table 9 Miscellaneous (14 Pins) (cont’d) Pin or Name Pin Ball Type No TEST I 38 SCAN_MD I Data Sheet Buffer Function Type 25M Crystal Input 25M Crystal Input. Variation is limited to ...
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Function Description The NINJA C/CX (ADM6992C/CX) integrates two 100Base-X physical layer devices (PHY), two complete 10BaseT modules, a two-port 10/100 switch controller and memory into a single chip for both 10Mbps and 100 Mbps Ethernet switch operation. It also ...
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Auto Negotiation and Speed Configuration 3.2.1 Auto Negotiation The Auto Negotiation function provides a mechanism for exchanging configuration information between two ends of a link segment and automatically selecting the highest performance mode of operations supported by both devices. ...
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These pins are also used for evaluating the default value in the base mode control register (register 0 ) according order to make these pins have the same Read/Write priority as software, they ...
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Modified Cut-through Mode The NINJA C/CX (ADM6992C/CX) begins to forward the received packet when it receives the first 64 bytes of the packet. The latency is about 512 bits time width. The NINJA C/CX (ADM6992C/CX) will not forward fragment ...
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Address Recognition and Packet Forwarding The address learning & filtering process forwards the incoming packets between bridged ports according to the Destination Address (DA) as below the UNICAST address and the address was found ...
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NINJA C/CX (ADM6992C/CX) to prevent the back pressure function causing HUB partition under a heavy traffic environment and reduce the packet lost rate to increase the whole system performance. 3.4.10 Full Duplex Flow Control When ...
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NINJA C/CX (NINJA C/CX (ADM6992C/CX)) Media Converter is connected. This link loss can then be sensed and reported by a Network Management agent in the remote UTP port’s host equipment. This feature will affect the NINJA C/CX (NINJA C/CX (ADM6992C/CX)) ...
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Figure 4 SMI Write Operation 3.6.1 Preamble Suppression The SMI of NINJA C/CX (ADM6992C/CX) supports a preamble suppression mode. If the station management entity (i.e. MAC or other management controller) determines that all devices which are connected to the same ...
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Write EEPROM Register via SMI Register To write data into desired EEPROM Register, write the address of the EEPROM Register. EX. <35”1”s><01><01><00000><00100><10><001 0000000 000001 0001000001000000> Write NINJA C/CX (ADM6992C/CX) Internal EEPROM mapping Reg.1 3.7 Reset Operation The NINJA C/CX ...
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Registers Description This chapter describes descriptions of EEPROM Registers and Serial Management Registers. 4.1 EEPROM Registers Table 12 EEPROM Register Map Register Bit 15 ...
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Table 12 EEPROM Register Map (cont’d) Register Bit 15 ...
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EEPROM Register Descriptions Table 13 Registers Address SpaceRegisters Address Space Module Base Address EEPROM 00 H Table 14 Registers Overview Register Short Name Register Long Name SR Signature Register PCR_0 Port Configuration Register 0 PCR_1 Port Configuration Register 1 ...
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Table 14 Registers Overview (cont’d) Register Short Name Register Long Name FR_9 Filter Register 9 FR_10 Filter Register 10 FR_11 Filter Register 11 FR_12 Filter Register 12 FR_13 Filter Register 13 FR_14 Filter Register 14 FR_15 Filter Register 15 PB_ID_0_0 ...
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Table 15 Register Access Types (cont’d) Mode Symbol Description HW Latch high, lhsc Latches high signal at high level, clear self clearing on read Latch low, llsc Latches high signal at low-level, clear self clearing on read Latch high, lhmk ...
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Field Bits Type Signature 15:0 ro Port Configuration Register 0 PCR_0 Port Configuration Register 0 Field Bits Type LBC 15 rw PAC 14 rw RPT 13 rw OPTC 12 rw MAC 11:7 rw ANPD ANA ...
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Field Bits Type ANE Port Configuration Register 1 PCR_1 Port Configuration Register 1 Field Bits Type LBC 15 rw PAC 14 rw RPT 13 rw OPTC 12 rw MAC 11:7 rw ANPD ...
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Field Bits Type ANA ANE Miscellaneous Configuration 0 MC_0 Miscellaneous Configuration 0 Field Bits Type ECRC 15 rw CRS 14 rw MPS 13:0 rw Miscellaneous Configuration Register ...
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MCR_1 Miscellaneous Configuration Register 1 Field Bits Type LED_ST 15 rw LED_ON 14 rw MAC 13 rw PFRC 12 rw Res 11 ro VLAN 10 rw EFM_P0 DBO Data Sheet ...
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Field Bits Type Res 4:0 ro Miscellaneous Configuration Register2 MCR_2 Miscellaneous Configuration Register 2 Field Bits Type Res 13 ro P0_MDI 12 rw XOVEN 11 rw FCDIS 10 rw RECHALF 9 ...
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Field Bits Type ANDIS 7 rw Res 6 ro Res 5:4 ro FPC 3 rw Cut 2 rw Res 1 ro Res 0 ro Buffer Management Configuration 0 BMC_0 Buffer Management Configuration 0 Field Bits Type Res 15:0 ro Buffer ...
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Field Bits Type Res 15:0 ro Buffer Management Configuration 2 BMC_2 Buffer Management Configuration 2 Field Bits Type Res 15:0 ro Ingress Bandwidth Control Configuration 0 IBW_CCR_0 Ingress Bandwidth Control Configuration 0 Field Bits Type IBC_P0 15 rw IBCT_P0 14:0 ...
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Field Bits Type EBC_P0 15 rw EBCT_P0 14:0 rw Ingress Bandwidth Control Configuration 2 IBW_CCR_2 Ingress Bandwidth Control Configuration 2 Field Bits Type IBC_P1 15 rw IBCT_P1 14:0 rw Egress Bandwidth Control Configuration 3 EBW_CCR_3 Egress Bandwidth Control Configuration 3 ...
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Field Bits Type EBC_P1 15 rw EBCT_P1 14:0 rw PHY Miscellaneous Configuration PHY_MC PHY Miscellaneous Configuration Field Bits Type Res 15:0 ro Data Sheet Description Port 1 Egress Bandwidth Control 0 D, Disable (Default Enable B Port ...
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Reserved MAC Address Filtering Configuration MAC_AFC MAC Address Filtering Configuration Field Bits Type MFM 15:14 rw TUFM 13:12 rw Res 11 ro CRC 10 ro Res 9:8 ro PFM_10 7:6 rw PFM_02 5:4 ro PFM_01 3:2 rw PFM_00 1:0 rw ...
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Packet Filter Control Registers 1 and 0 PCFC_1_0 Packet Filter Control Register 1 and 0 Field Bits Type Res 15 ro AP1_R1 14 ro AP0_R1 13 ro OPC_1A 12:8 ro Res 7 ro AP1_R1 6 rw AP1_R1 5 rw OPC_19 ...
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Filter Type Register 0 TFTR_0 Filter Type Register 0 Field Bits Type TF_7_15 15:14 rw TF_6_14 13:12 rw TF_5_13 11:10 rw TF_4_12 9:8 rw TF_3_11 7:6 rw TF_2_10 5:4 rw TF_1_9 3:2 rw TF_0_8 1:0 rw Filter Type Register 1 ...
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Filter Register 0 FR_0 Filter Register 0 Field Bits Type Filter 15:0 rw Other Filter Registers have the same structure and characteristics as listed in Table 18. Table 18 Other Filter Regsiters Register Short Name Register Long Name FR_1 Filter ...
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Port Base VLAN ID and Mask 0 of Port 0 PB_ID_0_0 Port Base VLAN ID and Mask 0 of Port 0 Field Bits Type DPRI 15:13 rw DCFI 12 rw PVID 11:10 rw Port Base VLAN ID and Mask 0 ...
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Port Base VLAN ID and Mask 0 of Port 1 PB_ID_0_1 Port Base VLAN ID and Mask 0 of Port 1 Field Bits Type DPRI 15:13 rw DCFI 12 rw PVID 11:10 rw Port Base VLAN ID and Mask 1 ...
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Tag Port Rule 0 Register 0 TPR_0_0 Tag Port Rule 0 Register 0 Field Bits Type Rule_Mask 15:12 rw Rule 11:0 rw Other Tag Port Rule 0 Registers have the same structure and characteristics as offset addresses are listed in ...
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Other Tag Port Rule 1 Registers have the same structure and characteristics as offset addresses are listed in Table Table 20 Other Tag Port Rule 1 Regsiters Register Short Name Register Long Name TPR_1_1 Tag Port Rule 1 Register 1 ...
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Field Bits Type TS_Def 15:12 rw TS_C 11 rw PRMT 10 RCSO 6 rw RCSF 5 rw U_LU 4 rw U_LD 3 rw TXF 2 rw SNFC Data Sheet Description TS-1000 ...
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OAM Configuration Register 2 NINJA C/CX (ADM6992C/CX) OAM C field Bit[8:15] definition for Remote Control OAM_CR_2 OAM Configuration Register 2 Field Bits Type RC_EF 15:8 rw RC_SF 7:0 rw Miscellaneous Configuration Register 3 Vender ID MCR_3 Miscellaneous Configuration Register 3 ...
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Miscellaneous Configuration Register 4 MCR_4 Miscellaneous Configuration 4 Field Bits Type MN_7_0 15:8 rw VID_23_16 7:0 rw Miscellaneous Configuration Register 5 MCR_5 Miscellaneous Configuration Register 5 Field Bits Type MN_23_8 15:0 rw Data Sheet Offset 38 H Description NTT TS-1000 ...
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Forwarding Configuration 1 FC_1 Forwarding Configuration 1 Field Bits Type Res 15:4 ro FM_C 3:2 rw Res Forwarding Configuration 2 FC_2 Forwarding Configuration 2 Field Bits Type Res 15:0 ro Data Sheet Offset 3A H ...
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Default Value Control Register DV_CR Default Value Control Register Field Bits Type PU_M 15 rw PS_D 14 rw PS_C 13 rw PM_T 12 rw IPG 11 rw IP_D 10 rw IP_F ...
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Field Bits Type FX1 5 rw FX_0 4 rw LED_2 3 rw LED_1 2 rw LED_0 1 rw DIS 0 rw 4.3 Serial Management Registers Table 21 Serial Management Register Map Register ...
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Table 21 Serial Management Register Map (cont’d) Register Source Address of Loop Back Test User Frame Source Address of Loop Back Test User Frame ...
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Serial Management Register Descriptions Table 22 Registers Address Space Module Base Address Serial 00 H Table 23 Registers Overview Register Short Name Register Long Name Chip_ID Chip Identifier OFR Overflow Flag Register PCNR_0 Port 0 Counter Register P0RBC P0 ...
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Table 24 Register Access Types Mode Symbol Description HW read/write rw Register is used as input for the HW read r Register is written by HW (register between input and output -> one cycle delay) Read only ro Register is ...
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Chip_ID Chip Identifier Field Bits Type P_Code 31:4 ro R_Code 3:0 ro Overflow Flag Register OFR Overflow Flag Register Field Bits Type P1CC 11 lhsc P1EC 10 lhsc P1TC 9 lhsc P1TP 8 lhsc P1RC 7 lhsc P1RP 6 lhsc ...
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Field Bits Type P0TP 2 lhsc P0RC 1 lhsc P0RP 0 lhsc Port 0 Counter Register PCNR_0 Port 0 Counter Register Field Bits Type Counter 31:0 rw Other Counter Registers have the same structure and characteristics as offset addresses are ...
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PCRR Port Counter Reset Register Field Bits Type RP1 1 rw RP0 0 rw Data Sheet Offset 0E H Description Reset All Counter of Port 1 1 RP1, Reset B Reset All Counter of Port 0 1 RP0, Reset B ...
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Hardware Setting Status Register HW_SSR Hardware Setting Status Register Field Bits Type BOD 24 ro BOB 22:20 ro DBP 18: 15:14 ro DAL ...
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Interrupt Register INT Interrupt Register Field Bits Type FMC 15 lhsc MTD 14 lhsc MFF 13 lhsc RUF 12 lhsc ROF 11 lhsc UVO 10 lhsc KVO 9 lhsc CO 8 lhsc P1F 7 lhsc P1D 6 lhsc P1S 5 ...
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Field Bits Type P0L 0 lhsc Interrupt Mask Register INT_M Interrupt Mask Register Field Bits Type FMC 15 rw MTD 14 rw MFCF 13 rw RUF 12 rw ROF 11 rw UVO 10 rw KVO ...
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Field Bits Type P1D 6 rw P1S 5 rw P1L 4 rw P0F 3 rw P0D 2 rw P0S 1 rw P0L 0 rw Data Sheet Description Port 1 Duplex Change 0 D, Disable Enable B Port ...
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Port Status Register PSR Port Status Register Field Bits Type L1 15:14 ro BRK1 12:11 ro BRK0 10 ro BFS1 9 ro BFS0 8 ro FC1 7 ro DX1 LS1 4 ro ...
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Field Bits Type FC0 3 ro DX0 LS0 0 ro EEPROM Register File Access Control EE_RFAC EEPROM Register File Access Control Field Bits Type CMD 31:29 rw Res 28:22 rw ADD 21:16 rw DATA 15:0 ...
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OAM Control Register OAM_CR OAM Control Register Field Bits Type FCK 12 rw FCU LB_HC 8 EAM 2 rw Data Sheet Offset 14 H Description ...
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Field Bits Type EAC 1 rw EKO 0 rw Source Address of Loop Back Test User Frame 0 SA_F_0 Source Address of Loop Back Test User Frame 0 Field Bits Type Address 31:0 rw Data Sheet Description Enable Auto CRC ...
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Source Address of Loop Back Test User Frame 1 SA_F_1 Source Address of Loop Back Test User Frame 1 Field Bits Type Byte_Count 26:16 rw Source_Add 15:0 rw Transmit OAM Frame Register 0 TFR_0 Transmit OAM Frame Register 0 Field ...
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Field Bits Type M_Field 31:0 rw Transmit OAM Frame Register 2 TFR_2 Transmit OAM Frame Register 2 Field Bits Type CRC_Field 23:16 rw M_Field 15:0 rw Data Sheet Description M Field Bit [31:0] of OAM Frame Offset 19 H Description ...
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Received OAM Frame Register 0 RFR_0 Received OAM Frame Register 0 Field Bits Type S_Field 31:16 rw C_Field 15:0 rw Received OAM Frame Register 1 RFR_1 Received OAM Frame Register 1 Field Bits Type M_Field 31:16 rw Data Sheet Offset ...
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Received OAM Frame Register 2 RFR_2 Received OAM Frame Register 0 Field Bits Type CRC_Field 23:16 rw M_Field 15:0 rw OAM Frame Status Register OAM_FSR OAM Frame Status Register Field Bits Type CRC 10 rw FIFO 9:6 rw TEX 5 ...
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Field Bits Type Data Sheet Description Unknown Valid OAM Frame received Known Valid OAM Frame received 74 Ninja C/CX ADM6992C/CX Registers Description Rev. 1.02, 2005-11-25 ...
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Electrical Specification DC and AC. 5.1 DC Characterization Table 27 Electrical Absolute Maximum Rating Parameter Power Supply Input Voltage Output Voltage Storage Temperature Power Dissipation ESD Rating Table 28 Recommended Operating Conditions Parameter 1) Power Supply 2) Core Power ...
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Power on Reset Timing Figure 5 Power on Reset Timing Table 30 Power on Reset Timing Parameter RST Low Period Start of Idle Pulse Width EEPROM Interface Timing Figure 6 EEPROM Interface Timing Table 31 EEPROM Interface Timing Parameter EESK ...
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Table 31 EEPROM Interface Timing (cont’d) Parameter EEDI to EESK Rising Hold Time EESK Falling to EEDO Output Delay Time SMI Timing Figure 7 SMI Timing Table 32 SMI Timing Parameter SDC Period SDC Low Period SDC High Period SDIO ...
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Packaging 64 LQFP Packaging for NinjaC (ADM6992-C) Figure 8 64 pin LQFP Outside Dimension Data Sheet 78 Ninja C/CX ADM6992C/CX Packaging Rev. 1.02, 2005-11-25 ...
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Table 33 Dimensions for 64 Pin LQFP Outside Dimension Symbol Millimeter (mm) Min. A – 0.08 1 Θ 0° Θ 0° 1 Θ 11° ...
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References [1] [2] [3] [4] [5] [6] Data Sheet 80 Ninja C/CX ADM6992C/CX References Rev. 1.02, 2005-11-25 ...
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Terminology A B Data Sheet 81 Ninja C/CX ADM6992C/CX Terminology Rev. 1.02, 2005-11-25 ...
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Published by Infineon Technologies AG ...