PLRXXL-SC-S43-C1 JDS UNIPHASE, PLRXXL-SC-S43-C1 Datasheet - Page 3

• Manufacturer Part Number: PLRXXL-SC-S43-C1
• Manufacturer: JDS UNIPHASE

Specifications of PLRXXL-SC-S43-C1

• Number Of Receivers: 1
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Lead Free Status / RoHS Status: Supplier Unconfirmed

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The JDSU 10 Gb/s 850 nm XFP optical transceiver has several low-speed interface
connections including a 2-wire serial interface. These connections include; mod-
ule not ready (Mod_NR), module deselect (Mod_DeSel), Interrupt, transmitter
disable (TX_DIS), module absent (Mod_ABS), Receive Loss Of Signal (RX_LOS),
and power down/reset (P_Down/RST).
Two loopback modes are available through the two-wire serial interface. The
loopback modes are useful to facilitate stand-alone testing. In system loopback
mode, data recovered from the system side transmit interface is re-directed to the
system side receive interface. This facilitates system side test and debug. In net-
work loopback mode, data recovered from the line side receive interface (optics)
is looped to the line side transmitter output back to the fi ber.
Transmitter
The transmitter path converts 9.95 Gb/s, 10.3 Gb/s, 10.5 Gb/s, or 10.75 Gb/s NRZ
electrical data to a standard compliant optical signal. The transmitter accepts a
100 Ω differential 120 mV peak-to-peak to 1000 mV peak-to-peak 10 Gb/s CML
electrical signal on TD- and TD+ pins. This performance exceeds the XFI “Ziffy”
specifi cation in the XFP MSA INF8077i revision 4.5 and provides over 300 mm
(12 inches) reach on improved FR4 material (loss tangent of 0.016) and offers
greater fl exibility to system integrators for host board layout.
Inside the module, the differential signals pass through a signal conditioner with
equalization that compensates for losses and deterministic jitter present on the
input data stream. A reference clock input (RefCLK+, RefCLK-) is used by the
internal PLL to determine line rate and signal lock condition. The Tx clock cir-
cuit provides a lock alarm output, failure to lock results in Mod_NR asserted. The
output of the Tx signal conditioner is input to the laser driver circuit which trans-
forms the small swing digital voltage to an output modulation and bias current
that drives a directly modulated 850 nm VCSEL. The optical signal is engineered
to meet the IEEE802.3 2005 Clause 52 10GBASE-SR, 10GBASE-SW, and 10 GFC
specifi cations. Closed-loop control of the transmitted laser power over tempera-
ture and voltage variations is provided. An LC connectorized receptacle provides
the mechanical interface to the multi-mode fi ber plant.
Receiver
The receiver converts incoming DC balanced serial 9.95 Gb/s, 10.3 Gb/s, 10.5 Gb/s,
or 10.75 Gb/s NRZ optical data into serial XFI electrical data. An LC connector-
ized receptacle provides the mechanical interface to the multi-mode fi ber plant.
A high speed PIN photodiode converts the optical signal into a current which
is converted to a voltage in a high-gain transimpedance amplifi er. The amplifi ed
signal is passed to a signal conditioning IC that provides clock and data recovery.
Loss of signal, and signal lock detection is included in the receive circuitry that is
refl ected in the Mod_NR status pin. The recovered data is output on the RD+ and
RD- pins as a 100 Ω 250 mV peak-to-peak CML signal. The output signal meets
the XFP MSA requirements.
ROHS COMPLIANT XFP OPTICAL TRANSCEIVER – 850NM
FOR UP TO 300M REACH