PLRXPL-VC-S43-22-N JDS UNIPHASE, PLRXPL-VC-S43-22-N Datasheet - Page 4

• Manufacturer Part Number: PLRXPL-VC-S43-22-N
• Manufacturer: JDS UNIPHASE

Specifications of PLRXPL-VC-S43-22-N

• Number Of Receivers: 1
• Protocols Supported: IEEE 802.3
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.47V
• Operating Supply Voltage (min): 3.14V
• Pin Count: 20
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Supply Current: 110mA
• Lead Free Status / RoHS Status: Compliant

4
Notes


ported. Good impedance matching for the driver and receiver is required.


* Transmission lines should be 100 Ω differential traces. Vias and other transmission line discontinuities should be avoided. In order to meet the host TP1 output jitter and
TP4 jitter tolerance requirements it is recommended that the PHY has both transmitter pre-emphasis to equalize the transmitter traces and receiver equalization to equalize the
receiver traces. With appropriate transmitter pre-emphasis and receiver equalization, up to 8 dB of loss at 5 GHz can be tolerated.
** R5 and R6 are required when an Open Collector driver is used in place of CMOS or TTL drivers. 5 kΩ value is appropriate.
*** The value of R
capacitive loading at 100 kHz clock frequency.
Open Collector Driver
(RS0 Rx Rate Select)
(RS1 Tx Rate Select)
CMOS or TTL Driver
CMOS or TTL Driver
Power supply fi ltering components should be placed as close to the V
Receiver (Tx Fault)
PECL driver and receiver components will require biasing networks. Please consult application notes from suppliers of these components. CML I/O on the PHY are sup-
CMOS, TTL, or
Receiver (LOS)
Open Collector
Open Collector
SDA and SCL should be bi-directional open collector connections in order to implement serial ID in JDSU SFP+ transceiver modules.
(Tx Disable)
Bidirectional
Bidirectional
Mod_ABS
Power supply filter component values are provided on page 7.
R1/R2 and R3/R4 are normally included in the output and input of the PHY. Please check the application notes for the IC in use.
SDA
SCL
p
and R
q
10 kΩ
depend on the capacitive loading of these lines and the two wire interface clock frequency. See SFF-8431. A value of 10 kΩ is appropriate for 80 pF
Rq
Figure 2
10 kΩ
10 kΩ
Rp***
Vcc
***
Vcc
Vcc
Vcc
Vcc
R5 ∗∗
R6 ∗∗
Recommended application schematic for the 10 G SFP+ optical transceiver
Vcc
Vcc
Section 2
10 VeeR
1 VeeT
3 Tx Disable
4 SDA
5 SCL
6 MOD_ABS
2 Tx Fault
7 RS0
8 LOS
9 RS1
cc
pins of the host connector as possible for optimal performance.
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
VeeT 20
VeeT 17
VccT 16
VccR 15
VeeR 14
VeeR 11
RD+ 13
RD-
TD- 19
TD+ 18
12
Application Schematic
C3
C4
Z
*
= 100 Ω
C6
Z
*
Rx
= 100 Ω
Ry
C5
L1
L2
R1
R2
*
*
50 Ω
50 Ω
R4
50 Ω
R3
50 Ω
*
*
C2
Power Supply Filter
PECL Receiver
(RX DATA)
PECL Driver
(TX DATA)
C1
Vcc +3.3V
Input