PLRXPL-VC-S43-22-N JDS UNIPHASE, PLRXPL-VC-S43-22-N Datasheet - Page 7

• Manufacturer Part Number: PLRXPL-VC-S43-22-N
• Manufacturer: JDS UNIPHASE

Specifications of PLRXPL-VC-S43-22-N

• Number Of Receivers: 1
• Protocols Supported: IEEE 802.3
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.47V
• Operating Supply Voltage (min): 3.14V
• Pin Count: 20
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Supply Current: 110mA
• Lead Free Status / RoHS Status: Compliant

7
SFP+ Optical Transceiver Pin Descriptions
Pin Number
Receiver
8
10, 11, 14
12
13
15
7
Transmitter
3
1, 17, 20
2
16
18
19
9
Module Definition
4
5
6
Symbol
LOS
V
RD-
RD+
V
RS0
TX_Disable
V
TX_Fault
V
TD+
TD-
SDA
SCL
MOD_ABS
RS1
eeR
ccR
eeT
ccT
Name
Loss of Signal Out (OC)
Receiver Signal Ground
Receiver Negative
DATA Out (PECL)
Receiver Positive
DATA Out (PECL)
Receiver Power Supply
RX Rate Select (LVTTL)
Transmitter Disable In (LVTTL)
Transmitter Signal Ground
Transmitter Fault Out (OC)
Transmitter Power Supply
Transmitter Positive
DATA In (PECL)
Transmitter Negative
DATA In (PECL)
TX Rate Select (LVTTL)
Two-wire Serial Data
Two-wire Serial Clock
Module Absent
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPATIBLE
Description
Suffi cient optical signal for potential BER < 1x10
Insuffi cient optical signal for potential BER < 1x10
This pin is open collector compatible, and should be pulled up
to Host V
These pins should be connected to signal ground on the host board.
Light on = Logic “0” Output
Receiver DATA output is internally AC coupled and series
terminated with a 50 Ω resistor.
Light on = Logic “1” Output
Receiver DATA output is internally AC coupled and series
terminated with a 50 Ω resistor.
This pin should be connected to a filtered +3.3 V power supply
on the host board. See Application schematics on page 4 for
fi ltering suggestions.
This pin has an internal 30 kΩ pull-down to ground. A signal
on this pin will not affect module performance.
Logic “1” Input (or no connection) = Laser off
Logic “0” Input = Laser on
This pin is internally pulled up to V
These pins should be connected to signal ground on the host board.
Logic “1” Output = Laser Fault (Laser off before t_fault)
Logic “0” Output = Normal Operation
This pin is open collector compatible, and should be pulled up
to Host Vcc with a 10 kΩ resistor.
This pin should be connected to a filtered +3.3 V power supply
on the host board. See Application schematics on page 4 for
fi ltering suggestions.
Logic “1” Input = Light on
Transmitter DATA inputs are internally AC coupled and
terminated with a differential 100 Ω resistor.
Logic “0” Input = Light on
Transmitter DATA inputs are internally AC coupled and
terminated with a differential 100 Ω resistor.
This pin has an internal 30 kΩ pulldown to ground. A signal on
this pin will not affect module performance.
Serial ID with SFF 8472 Diagnostics.
Module defi nition pins should be pulled up to Host Vcc with
appropriate resistors for the speed and capacitive loading of the
bus. See SFF8431.
Serial ID with SFF 8472 Diagnostics.
Module defi nition pins should be pulled up to Host Vcc with
appropriate resistors for the speed and capacitive loading of the
bus. See SFF8431.
Pin should be pulled up to Host V
MOD_ABS is asserted “high” when the SFP+ module is
physically absent from the host slot.
cc
with a 10 kΩ resistor.
cc
ccT
with 10 kΩ resistor.
with a 10 kΩ resistor.
-12
-12
= Logic “0”
= Logic “1”