LAN83C185-JT Standard Microsystems (SMSC), LAN83C185-JT Datasheet - Page 33

• Manufacturer Part Number: LAN83C185-JT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN83C185-JT

• Lead Free Status / RoHS Status: Compliant

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
SMSC LAN83C185
5.1
5.2
REGISTER #
SMI Register Mapping
16
17
18
20
21
22
23
27
28
29
30
31
SMI Register Format
0
1
2
3
4
5
6
The following registers are supported (register numbers are in decimal):
The mode key is as follows:
RW = read/write,
SC = self clearing,
WO = write only,
RO = read only,
LH = latch high, clear on read of register,
LL = latch low, clear on read of register,
NASR = Not Affected by Software Reset
Basic Control Register
Basic Status Register
PHY Identifier 1
PHY Identifier 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
Auto-Negotiation Expansion Register
Silicon Revision Register
Mode Control/Status Register
Special Modes
TSTCNTL – Testability/Configuration Control
TSTREAD1 – Testability data Read for LSB
TSTREAD2 – Testability data Read for MSB
TSTWRITE – Testability/Configuration data Write
Control / Status Indication Register
Special internal testability controls
Interrupt Source Register
Interrupt Mask Register
PHY Special Control/Status Register
Table 5.33 SMI Register Mapping
DESCRIPTION
DATASHEET
33
Basic
Basic
Extended
Extended
Extended
Extended
Extended
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
GROUP
Revision 0.8 (06-12-08)