FWLXT9785BC.A4 Intel, FWLXT9785BC.A4 Datasheet - Page 161

• Manufacturer Part Number: FWLXT9785BC.A4
• Manufacturer: Intel

Specifications of FWLXT9785BC.A4

• Lead Free Status / RoHS Status: Not Compliant

4.14
4.14.1
Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
Link Hold-Off Overview
The PHY link is established as soon as the system platform powers-up. In many cases, the system
platform is not capable of supporting network operation until configuration firmware is loaded. It is
desirable in such cases to prevent the PHY from establishing a link until the system platform is
fully configured and ready for network operation. Link Hold-Off was incorporated into the
LXT9785 device to satisfy these requirements. Enabling Link Hold-Off disables the PHY Link
capability until the system platform is fully capable of supporting network operation. The feature is
enabled by hardware control at power-up or software control during normal operation.
Features
Link Hold-Off prevents the LXT9785 from establishing a link by disabling the analog transmit and
receive capability. The digital capabilities of the PHY are unaffected including register access and
LED operation. Link Hold-Off can be enabled by an external hardware pin for all ports or by
software register access for individual ports. When Link Hold-Off is enabled, the transmitter and
receiver on the selected ports are forced into software power-down mode (see
“Power-Down Mode” on page
packets through the PHY.
The hardware enabled Link Hold-Off is controlled by the LINKHOLD pin. Internal pull-down
resistors hold the pin in the inactive state. Connecting a 5k pull-up resistor to the pin enables the
feature at power-up reset or external hardware pin Reset. Once a PHY port is programmed as
desired, clearing Register bit 0.11 will re-enable that port. Each port must be individually re-
enabled.
When a port is software reset, by setting Register 0.15, the state of the hardware configuration pin
captured by the last hardware or power-up reset determines the default register values for the
specific function for that port. Link Hold-Off, once enabled by hardware configuration, is re-
enabled on a port by issuing a software reset for that port. It is not necessary to reset the entire PHY
or switch system to re-enable Link Hold-Off.
3. Poll Register bit 29.9. When this bit is set, the test is complete and Register bits 29.7:0 contain
4. Write 0x6C00h to Register 29. Setting these bits places the device in long cable Cable
5. Poll Register bit 29.9. When set, record the value of Register bits 29.7:0 if a fault is found.
6. If a fault is present, a calculation is used to determine the distance to the fault. Insert the
7. Normal PHY operation can be resumed by writing 0x4000h to Register 29 or by software or
a value used to determine if a cable fault was found and the distance to that fault. A value of
0xFFh indicates no fault was found. Any other value indicates a fault was found, that value
should be stored for later use.
Diagnostics mode.
smallest value recorded from Register bits 29.7:0 in steps 3 and 5 above into the following
formula:
Distance_to_Fault = (Reg29[7:0] - 3.5) / 1.16
Register bit 29.8 is set if the fault is detected as a short circuit and is cleared if the fault is
detected as an open circuit. Register bits 29.12:11 are cleared when read and are cleared during
the same read cycle when Register bit 29.9 is read, indicating a fault condition exists.
hardware reset. The test suite can be run again by resuming at step 2 above.
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
126) to block signal activity from establishing a link and passing
Section 4.5.3,
161