FWLXT9785BC.A4 Intel, FWLXT9785BC.A4 Datasheet - Page 192
FWLXT9785BC.A4
Manufacturer Part Number
FWLXT9785BC.A4
Description
Manufacturer
Intel
Datasheet
1.FWLXT9785BC.A4.pdf
(234 pages)
Specifications of FWLXT9785BC.A4
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 53. RMII - 100BASE-FX Receive Timing
Table 74. RMII - 100BASE-FX Receive Timing Parameters
RxData<1:0>, CRS_DV, RXER setup to
REFCLK rising edge
RxData<1:0>, CRS_DV, RXER hold from
REFCLK rising edge
Receive start of /J/ to CRS_DV asserted
Receive start of /T/ to CRS_DV de-asserted
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
3. Values and conditions from RMII Specification, Rev. 1.2.
testing.
100BASE-TX or 100BASE-FX).
RxData[1:0]
default configuration of 00 (32 bits of initial fill).
CRS_DV
REFCLK
TPFI
Parameter
3
3
t
3
Sym
t1
t2
t3
t4
t
1
Min
–
4
2
–
t
2
Typ
14
18
–
–
t
4
1
Max
14
14
18
25
Revision Date: 30-May-2006
Units
Document Number: 249241
BT
BT
ns
ns
2
2
Revision Number: 010
Conditions
Datasheet
Test
–
–
–
–
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