ICS1892YT IDT, Integrated Device Technology Inc, ICS1892YT Datasheet - Page 127
ICS1892YT
Manufacturer Part Number
ICS1892YT
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.ICS1892YT.pdf
(148 pages)
Specifications of ICS1892YT
Lead Free Status / RoHS Status
Not Compliant
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10.5.4 100M MII / 100M Stream Interface: Synchronous Transmit Timing
ICS1892, Rev. D, 2/26/01
TXD[3:0]
TXEN
TXER
TXCLK
Table 10-11
transmit timing (which consists of timings of signals on the TXD[3:0], TXEN, TXER, and TXCLK pins).
Figure 10-4
Table 10-11. 100M MII / 100M Stream Interface: Synchronous Transmit Timing
Figure 10-4. 100M MII / 100M Stream Interface Synchronous Transmit Timing Diagram
Period
Time
ICS1892
t1
t2
TXD[3:0], TXEN, TXER Setup to TXCLK Rise
TXD[3:0], TXEN, TXER Hold after TXCLK Rise
shows the timing diagram for the time periods.
lists the significant time periods for the 100M MII / 100M Stream Interface synchronous
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
Parameter
t1
t2
127
Conditions
Chapter 10 DC and AC Operating Conditions
–
–
Min.
15
0
Typ.
–
–
February 26, 2001
Max.
–
–
Units
ns
ns
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