ICS1892YT IDT, Integrated Device Technology Inc, ICS1892YT Datasheet - Page 136
ICS1892YT
Manufacturer Part Number
ICS1892YT
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.ICS1892YT.pdf
(148 pages)
Specifications of ICS1892YT
Lead Free Status / RoHS Status
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10.5.13 MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)
ICS1892, Rev. D, 2/26/01
Table 10-20
transmission. The time periods consist of timings of signals on the following pins: TXEN, TXCLK, and CRS.
Figure 10-13
Table 10-20. MII Carrier Assertion/De-Assertion (Half-Duplex Transmission Only)
Figure 10-13. MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only)
TXEN
TXCLK
CRS
Period
Time
t1
t2
t3
ICS1892 Data Sheet
TXEN Sampled Asserted to CRS Assert
TXEN Sampled De-Asserted to CRS De-Asserted
TXEN De-Asserted to CRS De-Asserted
lists the significant time periods for the MII carrier assertion/de-assertion during half-duplex
shows the timing diagram for the time periods.
t1
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
Parameter
136
t3
Conditions
Chapter 10 DC and AC Operating Conditions
–
–
–
t2
Min. Typ. Max.
–
–
–
< 1
< 1
–
February 26, 2001
1
1
4
Bit times
Units
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