ICS1892Y IDT, Integrated Device Technology Inc, ICS1892Y Datasheet - Page 135

• Manufacturer Part Number: ICS1892Y
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS1892Y

• Lead Free Status / RoHS Status: Not Compliant

10.5.12 MII / 100M Stream Interface: Transmit Latency
ICS1892, Rev. D, 2/26/01
TXEN
TXCLK
TXD
TP_TX*
*Shown
unscrambled.
Table 10-19
periods consist of timings of signals on the following pins: TXEN, TXCLK, TXD (that is, TXD[3:0]), and
TP_TX (that is, the TP_TXP and TP_TXN pins).
periods.
Table 10-19. MII / 100M Stream Interface Transmit Latency
† The IEEE maximum is 18 bit times.
Figure 10-12. MII / 100M Stream Interface Transmit Latency Timing Diagram
Period
Time
t1
t2
ICS1892
TXEN Sampled to MDI Output of First
Bit of /J/ †
TXD Sampled to MDI Output of First
Bit
lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time
Preamble /J/
Parameter
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
Preamble /K/
t1
t2
135
Figure 10-12
MII
100M Stream Interface
Conditions
shows the timing diagram for the time
Chapter 10 DC and AC Operating Conditions
Min.
–
–
Typ. Max.
4
4
February 26, 2001
4
4
Bit times
Bit times
Units