ICS1892Y IDT, Integrated Device Technology Inc, ICS1892Y Datasheet - Page 93

• Manufacturer Part Number: ICS1892Y
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS1892Y

• Lead Free Status / RoHS Status: Not Compliant

8.12.8 Halt Symbol (bit 17.6)
8.12.9 Premature End (bit 17.5)
8.12.10 Auto-Negotiation Complete (bit 17.4)
8.12.11 100Base-TX Signal Detect (bit 17.3)
8.12.12 Jabber Detect (bit 17.2)
ICS1892, Rev. D, 2/26/01
The Halt Symbol bit indicates to an STA the detection of an Halt Symbol in a 100Base data stream by the
ICS1892.
During reception of a valid packet, the ICS1892 examines each symbol to ensure that the data being
passed to the MAC/Repeater Interface is error free. In addition, it looks for special symbols such as the Halt
Symbol. If a Halt Symbol is encountered, the ICS1892 indicates this condition to the MAC/repeater.
If this bit is set to a logic:
•
•
This bit is a latching high bit. (For more information on latching high and latching low bits, see
8.1.4.1, “Latching High Bits”
Note:
The Premature End bit indicates to an STA the detection of two consecutive Idles in a 100Base data stream
by the ICS1892.
During reception of a valid packet, the ICS1892 examines each symbol to ensure that the data being
passed to the MAC/Repeater Interface is error free. If two consecutive Idles are encountered it indicates
this condition to the MAC/repeater by setting this bit.
If this bit is set to a logic:
•
•
This bit is a latching high bit. (For more information on latching high and latching low bits, see
8.1.4.1, “Latching High Bits”
Note:
The Auto-Negotiation Complete bit is used to indicate to an STA the completion of the Auto-Negotiation
process. When this bit is set to logic:
•
•
The 100Base-TX Signal Detect bit indicates either the presence or absence of a signal on the Twisted-Pair
Receive pins (TP_RXP and TP_RXN) in 100Base-TX mode. This bit is logic:
•
•
Bit 17.2 is functionally identical to bit 1.1. The Jabber Detect bit indicates whether a jabber condition has
occurred. This bit is a 10Base-T function.
Zero, it indicates a Halt Symbol has not been detected since the last read of this register.
One, it indicates a Halt Symbol was detected in the packet since the last read of this register.
Zero, it indicates a Premature End condition has not been detected since the last read of this register.
One, it indicates a Premature End condition was detected in the packet since the last read of this
register.
Zero, it indicates that the auto-negotiation process is either not complete or is disabled by the Control
Register’s Auto-Negotiation Enable bit (bit 0.12)
One, it indicates that the ICS1892 has completed the auto-negotiation process and that the contents of
Management Registers 4, 5, and 6 are valid.
Zero when no signal is detected on the Twisted-Pair Receive pins and logic.
One when a signal is present on these pins.
ICS1892
This bit has no definition in 10Base-T mode.
This bit has no definition in 10Base-T mode.
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
and
and
Section 8.1.4.2, “Latching Low
Section 8.1.4.2, “Latching Low
93
Bits”.)
Bits”.)
Chapter 8 Management Register Set
February 26, 2001
Section
Section