CYP15G0402DXB-BGI Cypress Semiconductor Corp, CYP15G0402DXB-BGI Datasheet - Page 24
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CYP15G0402DXB-BGI
Manufacturer Part Number
CYP15G0402DXB-BGI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CYP15G0402DXB-BGI.pdf
(29 pages)
Specifications of CYP15G0402DXB-BGI
Lead Free Status / RoHS Status
Not Compliant
Document #: 38-02057 Rev. *G
CYP(V)15G0402DXB HOTLink II Transmitter Switching Waveforms
Notes:
34. When REFCLK is configured for half-rate operation (TXRATE = HIGH) and data is captured using REFCLK instead of a TXCLKx clock (TXCKSEL = LOW), data
35. The TXCLKO output is at twice the rate of REFCLK when TXRATE = HIGH and same rate as REFCLK when TXRATE = LOW. TXCLKO does not follow the
36. The rising edge of TXCLKO output has no direct phase relationship to the REFCLK input.
Transmit Interface
TXCLKO Timing
TXCKSEL = LOW
TXRATE = HIGH
Transmit Interface
Write Timing
TXCKSEL = LOW
TXRATE = HIGH
Transmit Interface
Write Timing
TXCKSEL = LOW
TXRATE = LOW
TXDx[9:0],
is captured using both the rising and falling edges of REFCLK.
duty cycle of REFCLK.
TXDx[9:0],
REFCLK
TXDx[9:0],
Transmit Interface
Write Timing
TXCKSEL ≠ LOW
TXOPx
REFCLK
TXCLKx
REFCLK
TXOPx,
TXOPx
TXCLKO
Note 36
Note 34
t
TXCLKOD+
t
t
TREFDH
REFH
t
TXCLKH
t
TXCLKO
t
t
REFCLK
REFH
t
REFH
t
TXCLK
t
Note 35
TXCLKOD–
t
TREFDS
t
REFL
t
TXCLKL
t
TXDS
t
TREFDS
t
REFCLK
t
REFCLK
Note 34
t
TREFDH
t
TXDH
t
TREFDH
t
REFL
t
REFL
t
CYP15G0402DXB
CYV15G0402DXB
TREFDS
Page 24 of 29
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