CYV15G0201DXB-BBI Cypress Semiconductor Corp, CYV15G0201DXB-BBI Datasheet - Page 31

• Manufacturer Part Number: CYV15G0201DXB-BBI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYV15G0201DXB-BBI

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02058 Rev. *H
CYP(V)(W)15G0201DXB AC Characteristics
Transmitter LVTTL Switching Characteristics
f
t
t
t
t
t
t
t
f
t
t
t
Receiver LVTTL Switching Characteristics
f
t
t
t
t
t
t
t
t
REFCLK Switching Characteristics Over the Operating Range
f
t
t
t
t
t
t
t
t
Notes:
28. This parameter is 154 MHz for CYW15G0201DXB.
29. This parameter is 6.49 ns for CYW15G0201DXB.
30. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
31. The ratio of rise time to falling time must not vary by greater than 2:1.
32. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
33. Parallel data output specifications are only valid if all inputs or outputs are loaded with similar DC and AC loads.
34. The duty cycle specification is a simultaneous condition with the t
TS
TXCLK
TXCLKH
TXCLKL
TXCLKR
TXCLKF
TXDS
TXDH
TOS
TXCLKO
TXCLKOD+
TXCLKOD–
RS
RXCLKP
RXCLKH
RXCLKL
RXCLKD
RXCLKR
RXCLKF
RXDV–
RXDV+
REF
REFCLK
REFH
REFL
REFD
REFR
REFF
TREFDS
TREFDH
Parameter
cannot be as large as 30%–70%.
[30, 31, 32]
[34]
[30, 31, 32]
[33]
[33]
[30]
[30]
[30, 31, 32]
[30]
[30]
[30, 31, 32]
TXCLKx Clock Frequency
TXCLKx Period
TXCLKx HIGH Time
TXCLKx LOW Time
TXCLKx Rise Time
TXCLKx Fall Time
Transmit Data Set-Up Time to TXCLKx↑ (TXCKSEL ≠ LOW)
Transmit Data Hold Time from TXCLKx↑ (TXCKSEL ≠ LOW)
TXCLKO Clock Frequency = 1x or 2x REFCLK Frequency
TXCLKO Period
TXCLKO+ Duty Cycle with 60% HIGH time
TXCLKO– Duty Cycle with 40% HIGH time
RXCLKx Clock Output Frequency
RXCLKx Period
RXCLKx HIGH Time (RXRATE = LOW)
RXCLKx HIGH Time (RXRATE = HIGH)
RXCLKx LOW Time (RXRATE = LOW)
RXCLKx LOW Time (RXRATE = HIGH)
RXCLKx Duty Cycle centered at 50%
RXCLKx Rise Time
RXCLKx Fall Time
Status and Data Valid Time to RXCLKx (RXCKSEL = HIGH or MID)
Status and Data Valid Time to RXCLKx (Half Rate Recovered Clock)
Status and Data Valid Time From RXCLKx (RXCKSEL = HIGH or MID)
Status and Data Valid Time From RXCLKx (Half Rate Recovered Clock)
REFCLK Clock Frequency
REFCLK Period
REFCLK HIGH Time (TXRATE = HIGH)
REFCLK HIGH Time (TXRATE = LOW)
REFCLK LOW Time (TXRATE = HIGH)
REFCLK LOW Time (TXRATE = LOW)
REFCLK Duty Cycle
REFCLK Rise Time (20% – 80%)
REFCLK Fall Time (20% – 80%)
Transmit Data Set-up Time to REFCLK (TXCKSEL = LOW)
Transmit Data Hold Time from REFCLK (TXCKSEL = LOW)
Description
REFH
Over the Operating Range
and t
REFL
parameters. This means that at faster character rates the REFCLK duty cycle
CYW15G0201DXB
CYP15G0201DXB
CYV15G0201DXB
5UI – 1.5
5UI – 1.0
5UI – 1.8
5UI – 2.3
6.66
6.66
6.66
2.33
2.33
6.66
2.9
2.9
Min.
19.5
19.5
–1.0
–0.5
9.75
5.66
5.66
–1.0
19.5
2.2
2.2
0.2
0.2
1.7
0.8
0.3
0.3
5.9
5.9
1.7
0.8
30
[30]
[30]
[29]
[29]
[29]
[30]
[30]
[29]
102.56
150
150
150
150
51.28
51.28
26.64
52.28
26.64
52.28
51.28
Max.
+0.5
+1.0
+1.0
Page 31 of 46
1.7
1.7
1.2
1.2
70
2
2
[28]
[28]
[28]
[28]
MHz
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
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