CYV15G0201DXB-BBI Cypress Semiconductor Corp, CYV15G0201DXB-BBI Datasheet - Page 7

• Manufacturer Part Number: CYV15G0201DXB-BBI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYV15G0201DXB-BBI

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02058 Rev. *H
Pin Descriptions
SCSEL
TXOPA
TXOPB
TXCKSEL
TXRATE
TXCLKO±
TXCLKA
TXCLKB
TXMODE[1:0] 3-Level Select
RXDA[7:0]
RXDB[7:0]
Note:
4.
Transmit Path Clock and Clock Control
Transmit Path Mode Control
Receive Path Data Signals
Pin Name
3-Level select inputs are used for static configuration. They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and HIGH.
The LOW level is usually implemented by direct connection to V
not connected or allowed to float, a 3-Level select input will self-bias to the MID level.
LVTTL Input,
synchronous,
internal pull-down,
sampled by
TXCLKA↑
or REFCLK↑
LVTTL Input,
synchronous,
internal pull-up,
sampled by the
respective TXCLKx↑
or REFCLK↑
3-Level Select
Static Control Input
LVTTL Input,
Static Control input,
internal pull-down
LVTTL Output
LVTTL Clock Input,
internal pull-down
Static Control inputs
LVTTL Output,
synchronous to the
selected RXCLKx↑
output or
REFCLK↑
I/O Characteristics
CYP(V)(W)15G0201DXB Dual HOTLink II Transceiver (continued)
[3]
input
[3]
[3]
[4]
[4]
Special Character Select. Used in some transmit modes along with TXCTx[1:0] to encode
special characters or to initiate a Word Sync Sequence. When the transmit paths are
configured for independent inputs clocks (TXCKSEL = MID), SCSEL is captured relative to
TXCLKA↑.
Transmit Path Odd Parity. When parity checking is enabled (PARCTL ≠ LOW), the parity
captured at these inputs is XORed with the data on the associated transmit data TXDx bus
to verify the integrity of the captured character.
Transmit Clock Select. Selects the clock source, used to write data into the Transmit Input
Register, of the transmit channel(s).
When LOW, both Input Registers are clocked by REFCLK↑
as the Input Register clock for TXDx[7:0] and TXCTx[1:0]. When HIGH, TXCLKA↑ is used
to clock data into the Input Register of each channel.
When TXCKSEL = MID or HIGH (TXCLKx or TXCLKA selected to clock input register),
configuring TXRATE = HIGH (Half-rate REFCLK) is an invalid mode of operation.
Transmit PLL Clock Rate Select. When TXRATE = HIGH, the Transmit PLL multiplies
REFCLK by 20 to generate the serial symbol-rate clock. When TXRATE = LOW, the transmit
PLL multiples REFCLK by 10 to generate the serial symbol-rate clock. See Table 10 for a
list of operating serial rates.
When REFCLK is selected to clock the receive parallel interfaces (RXCKSEL = LOW), the
TXRATE input also determines if the clocks on the RXCLKA± and RXCLKC± outputs are
full or half-rate. When TXRATE = HIGH (REFCLK is half-rate), the RXCLKA± and RXCLKC±
output clocks are also half-rate clocks and follow the frequency and duty cycle of the
REFCLK input. When TXRATE = LOW (REFCLK is full-rate), the RXCLKA± and RXCLKC±
output clocks are full-rate clocks and follow the frequency and duty cycle of the REFCLK
input.
When TXCKSEL = MID or HIGH (TXCLKx or TXCLKA selected to clock input register),
configuring TXRATE = HIGH (Half-rate REFCLK) is an invalid mode of operation.
Transmit Clock Output. This true and complement output clock is synthesized by the
transmit PLL and operates synchronous to the internal transmit character clock. It operates
at either the same frequency as REFCLK (when TXRATE = LOW), or at twice the frequency
of REFCLK (when TXRATE = HIGH). This output clock has no direct phase relationship to
REFCLK.
Transmit Path Input Clocks. These clocks must be frequency-coherent to TXCLKO±, but
may be offset in phase. The internal operating phase of each input clock (relative to
REFLCK or TXCLKO±) is adjusted when TXRST = LOW and locked when TXRST = HIGH.
Transmit Operating Mode. These inputs are interpreted to select one of nine operating
modes of the transmit path. See Table 3 for a list of operating modes.
Parallel Data Output. These outputs change following the rising edge of the selected
receive interface clock.
When the Decoder is enabled (DECMODE = HIGH or MID), these outputs represent either
received data or special characters. The status of the received data is represented by the
values of RXSTx[2:0]. When the Decoder is bypassed (DECMODE = LOW), RXDx[7:0]
become the higher order bits of the 10-bit received character. See Table 16 for details.
SS
(ground). The HIGH level is usually implemented by direct connection to V
Signal Description
[3]
CYW15G0201DXB
CYP15G0201DXB
CYV15G0201DXB
. When MID, TXCLKx↑ is used
CC
Page 7 of 46
(power). When
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