1892YLF IDT, Integrated Device Technology Inc, 1892YLF Datasheet - Page 138

• Manufacturer Part Number: 1892YLF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 1892YLF

• Lead Free Status / RoHS Status: Compliant

10.5.15 Media Dependent Interface: Input-to-Carrier Assertion/De-Assertion
ICS1892, Rev. D, 2/26/01
TP_RX*
CRS
COL
*Shown
unscrambled.
Table 10-22
periods consist of timings of signals on the following pins: CRS, COL, and TP_RX (that is, the TP_RXP and
TP_RXN pins).
Table 10-22. MDI Input-to-Carrier Assertion/De-Assertion Timing
† The IEEE maximum is 20 bit times.
‡ The IEEE minimum is 13 bit times, and the maximum is 24 bit times.
Figure 10-15. MDI Input to Carrier Assertion / De-Assertion Timing Diagram
Period
Time
t1
t2
t3
t4
ICS1892 Data Sheet
First Bit of /J/ into TP_RX to CRS
Assert †
First Bit of /J/ into TP_RX while
Transmitting Data to COL Assert †
First Bit of /T/ into TP_RX to CRS
De-Assert ‡
First Bit of /T/ Received into TP_RX to
COL De-Assert ‡
lists the significant time periods for the MDI input-to-carrier assertion/de-assertion. The time
Figure 10-15
First bit
t2
Parameter
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
t1
shows the timing diagram for the time periods.
138
Half-Duplex Mode
Half-Duplex Mode
Conditions
–
–
Chapter 10 DC and AC Operating Conditions
First bit of /T/
t3
t4
Min.
13
9
9
–
Typ.
–
–
–
–
Max.
February 26, 2001
13
13
17
14
Bit times
Bit times
Bit times
Bit times
Units