IDT82V1671AJ IDT, Integrated Device Technology Inc, IDT82V1671AJ Datasheet - Page 71

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IDT82V1671AJ

Manufacturer Part Number
IDT82V1671AJ
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT82V1671AJ

Number Of Channels
4
On-hook Transmission
Yes
Polarity Reversal
Yes
On-chip Ring Relay Driver
Yes
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
PLCC
Operating Temperature Classification
Industrial
Pin Count
28
Mounting
Surface Mount
Operating Current
95mA
Operating Supply Voltage (max)
3.465V
Operating Supply Voltage (min)
3.135V
Lead Free Status / RoHS Status
Compliant
RSLIC & CODEC CHIPSET
GREG21: FSK Seizure Length Register, Read/Write (34H/B4H)
GREG22: FSK Mark Length Register, Read/Write (35H/B5H)
GREG23: FSK Transmit Start, Mark_after_send, Modulation Standard, FSK Channel Selection, FSK enable, Read/Write (36H/B6H)
The default value of 0 means that no data bytes will be sent out.
The seizure length is the number of '01' pairs that represent the seizure phase.
The seizure length is two times of the value of the FSK_SL[7:0] bits. The value of the FSK_SL[7:0] bits is valid from 0 to 255(d), corre-
sponding to the seizure length from 0 to 510 (d).
The default value of this register is 0, that means no seizure signal will be sent out.
The mark signal is a stream of '1' that will be transmitted in initial flag phase.
This register is used to set the number of the mark bits ‘1’. The value of the FSK_ML[7:0] bits is valid from 0 to 255(d).
The default value of 0 means that no mark signal will be sent out.
FSK_CS
FSK_EN
FSK_BS
FSK_MAS
FSK_TS
Command
Command
Command
I/O data
I/O data
I/O data
FSK channel selection. The FSK_CS[1:0] bits select a channel on which the FSK signal is generated.
FSK_CS[1:0] = 00: Channel 1 is selected (default);
FSK_CS[1:0] = 01: Channel 2 is selected;
FSK_CS[1:0] = 10: Channel 3 is selected;
FSK_CS[1:0] = 11: Channel 4 is selected.
FSK function block enable.
FSK_EN = 0:
FSK_EN = 1:
FSK modulation standard selection
FSK_BS = 0:
FSK_BS = 1:
Mark After Send. The FSK_MAS bit determines whether the FSK generator will keep on sending a mark-after-send sig-
nal (a string of ‘1’) after finish sending the data in the FSK-RAM.
FSK_MAS = 0:
FSK_MAS = 1:
FSK transmission starts.
FSK_TS = 0:
FSK_TS = 1:
R/W
R/W
R/W
b7
b7
b7
Reserved
b6
b6
b6
0
0
0
FSK function block is disabled (default);
FSK function block is enabled.
BELL 202 standard is selected (default);
ITU-T V.23 standard is selected.
The FSK output will be muted after sending out the data in the FSK-RAM (default);
The FSK generator sends out a mark-after-send signal after finish sending out the data in the FSK-
RAM. This signal will be stopped if the FSK_MAS bit is set to 0.
FSK transmission is disabled (default);
FSK transmission starts.
The FSK_TS bit will be reset automatically after the data in the FSK-RAM is finished sending. If the
seizure length, the mark length and the data length are set to 0, the FSK_TS bit will be reset to 0
immediately after it is set to 1.
b5
b5
b5
1
1
1
FSK_CS[1:0]
71
b4
b4
b4
1
1
1
FSK_ML[7:0]
FSK_SL[7:0]
FSK_EN
b3
b3
b3
0
0
0
FSK_BS
b2
b2
b2
1
1
1
IDT82V1671/IDT82V1671A, IDT82V1074
FSK_MAS
b1
b1
b1
0
0
1
FSK_TS
b0
b0
b0
0
1
0

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