IDT82V1671AJ IDT, Integrated Device Technology Inc, IDT82V1671AJ Datasheet - Page 91

• Manufacturer Part Number: IDT82V1671AJ
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V1671AJ

• Number Of Channels: 4
• On-hook Transmission: Yes
• Polarity Reversal: Yes
• On-chip Ring Relay Driver: Yes
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: PLCC
• Operating Temperature Classification: Industrial
• Pin Count: 28
• Mounting: Surface Mount
• Operating Current: 95mA
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Lead Free Status / RoHS Status: Compliant

four bits IO[3] to IO[0] have their respective mask bits - IO_M[3] to
IO_M[0] in LREG19. Each change of the IO[n] bit will generate an
interrupt if its mask bit IO_M[n] is set to 0 (n = 0 to 3).
6.4
the following event:
Table - 27 Interrupt Source and Interrupt Mask
level if any interrupt is generated. In GCI mode, if any interrupt is
generated in a channel, the corresponding INT_CHA or INT_CHB bit in
upstream C/I channel will be set to active level. The valid polarity of the
INT/INT pin and the INT_CHA, INT_CHB bits is determined by the
INT_POL bit in register GREG24 as shown below:
a read operation on the corresponding interrupt register. For example,
reading GREG26 clears the interrupts generated by hook/ring trip
detection and ground-key detection. Additionally, the CODEC provides a
dedicated command to clear all the interrupts at one time. That is, by
applying a write operation to GREG26, all the global and local interrupt
Hook Status
Ground-key Status
Ring Trip Status
RSLIC IO Status
Ground-key Polarity
Over Temperature Status
Ramp Generation
UTD Result
Level Meter Sequence
RSLIC & CODEC CHIPSET
The debounced IO data are stored in the IO[3:0] bits in LREG20. The
The RSLIC-CODEC chipset is capable of generating interrupts for
• Off-hook/on-hook detected
• ground-key detected
• ground-key polarity changed
• Ring trip detected
• IO status changed
• Over temperature detected
In MPI mode, the interrupt output pin INT/INT will be set to active
INT_POL = 0: active low;
INT_POL = 1: active high.
In both MPI and GCI mode, the pending interrupts can be cleared by
Interrupt Source
INTERRUPT HANDLING
IO[n] bit in LREG20 (n = 0 to 3)
HK[n] bit in GREG26 (n = 0 to 3)
GK[n] bit in GREG26 (n = 0 to 3)
HK[n] bit in GREG26 (n = 0 to 3)
GK_POL bit in LREG21
OTMP bit in LREG21
RAMP_OK bit in LREG21
UTD_OK bit in LREG21
LM_OK bit in LREG21
Status bits
Each change of the HK[n] bit
Each change of the GK[n] bit
Each change of the HK[n] bit
Each change of the GK_POL bit
A change of the OTMP bit from 0 to 1
A change of the UTD_OK bit from 0 to 1
A change of the LM_OK bit from 0 to 1
Each change of the IO[n] bit when the corresponding IO
pin is configured as an input
A change of the RAMP_OK bit from 0 to 1
Interrupt Generating Conditions
91
ring trip detection and ground-key detection for four channels (two bits
per channel). Other interrupt status of each channel is contained by the
respective interrupt status registers LREG20 and LREG21 (each
interrupt function has one bit). These bits are set when an interrupt is
pending for the associated source. Two interrupt mask registers
(LREG18 and LREG19) per channel contain one mask bit for each of
the above interrupt functions except special tone detected and level
metering completed. If a mask bit is set to high, the corresponding
interrupt will be masked. Refer to
status registers will be cleared.
status registers and resets the INT/INT pin to inactive (MPI mode) or
resets the INT_CHA and INT_CHB bits in the GCI C/I channel (GCI
mode). A software reset applied to one channel clears all local interrupt
status registers of that channel but does not effect those of the other
channels and the global interrupt status register.
6.5
paths and the integrated analog and digital loopbacks inside the
CODEC. Refer to the register descriptions on GREG6 and LREG3 for
details.
• Level metering finished
• Special tone detected
• Ramp generation finished
The interrupt status register GREG26 contains the results of hook/
A hardware or power-on reset of the CODEC clears all interrupt
Figure - 42
SIGNAL PATH AND TEST LOOPBACKS
on the following page shows the main AC and DC signal
IDT82V1671/IDT82V1671A, IDT82V1074
Table - 27
HK_M bit in LREG18
GK_M bit in LREG18
HK_M bit in LREG18
IO_M[n] bit in LREG19
GKP_M bit in LREG18
OTMP_M bit in LREG18
RAMP_M bit in LREG18
None
None
for detailed information.
Mask Bit