XC5VLX50-1FFG324C Xilinx Inc, XC5VLX50-1FFG324C Datasheet - Page 197
![FPGA, VIRTEX-5 LX, 50K, 324FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50-1FFG324C
Manufacturer Part Number
XC5VLX50-1FFG324C
Description
FPGA, VIRTEX-5 LX, 50K, 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50-1FFG324C
No. Of Logic Blocks
7200
Family Type
Virtex-5
No. Of Speed Grades
1
Total Ram Bits
1769472
No. Of I/o's
220
Clock Management
DCM, PLL
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-BBGA, FCBGA
Core Supply Voltage Range
1V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1562
Available stocks
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Quantity
Price
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XC5VLX50-1FFG324C
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- XC5VLX30-1FFG324C PDF datasheet
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X-Ref Target - Figure 5-22
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
SEL D [1:0], DATA D [3:0]
SEL C [1:0], DATA C [3:0]
SEL B [1:0], DATA B [3:0]
SEL A [1:0], DATA A [3:0]
8:1 Multiplexer
Each slice has an F7AMUX and an F7BMUX. These two muxes combine the output of two
LUTs to form a combinatorial function up to 13 inputs (or an 8:1 MUX). Up to two 8:1
MUXes can be implemented in a slice, as shown in
SELF7(1)
SELF7(2)
Input (1)
Input (1)
Input (2)
Input (2)
CLK
Figure 5-22: Two 8:1 Multiplexers in a Slice
(D[6:1])
(C[6:1])
(B[6:1])
(A[6:1])
(CLK)
(CX)
(AX)
6
6
6
6
A[6:1]
A[6:1]
A[6:1]
A[6:1]
www.xilinx.com
LUT
LUT
LUT
LUT
O6
O6
O6
O6
SLICE
F7BMUX
F7AMUX
Figure
(Optional)
(Optional)
D Q
D Q
(CMUX)
(AMUX)
5-22.
(CQ)
(AQ)
UG190_5_22_090806
8:1 MUX
Output (1)
Registered
Output
8:1 MUX
Output (2)
Registered
Output
CLB Overview
197
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