XC5VLX50-1FFG324C Xilinx Inc, XC5VLX50-1FFG324C Datasheet - Page 42

• Manufacturer Part Number: XC5VLX50-1FFG324C
• Description: FPGA, VIRTEX-5 LX, 50K, 324FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG324C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 1769472
• No. Of I/o's: 220
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 220
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 324-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1562

Chapter 1: Clock Resources
42
Regional Clock Buffer - BUFR
X-Ref Target - Figure 1-19
The regional clock buffer (BUFR) is another clock buffer available in Virtex-5 devices.
BUFRs drive clock signals to a dedicated clock net within a clock region, independent from
Clock Capable I/O
Clock Capable I/O
Clock Capable I/O
Clock Capable I/O
Not all available BUFIOs are shown.
Figure 1-19: BUFIO Driving I/O Logic In a Single Clock Region
P
P
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N
www.xilinx.com
I/O
I/O
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I/O
I/O
I/O
I/O
I/O
I/O
I/O
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I/O
I/O
I/O
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I/O
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BUFIO
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BUFR
BUFR
To Adjacent
Region
To Adjacent
Region
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ug190_1_19_060706
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