MCP635T-E/MF Microchip Technology, MCP635T-E/MF Datasheet - Page 21

• Manufacturer Part Number: MCP635T-E/MF
• Description: Dual, 24MHz OP W /CS, E Temp 10 DFN 3x3mm T/R
• Manufacturer: Microchip Technology

Specifications of MCP635T-E/MF

• Amplifier Type: General Purpose
• Number Of Circuits: 2
• Output Type: Rail-to-Rail
• Slew Rate: 10 V/µs
• Gain Bandwidth Product: 24MHz
• Current - Input Bias: 4pA
• Voltage - Input Offset: 1800µV
• Current - Supply: 2.5mA
• Current - Output / Channel: 70mA
• Voltage - Supply, Single/dual (±): 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-DFN
• Number Of Channels: 2
• Voltage Gain Db: 124 dB
• Common Mode Rejection Ratio (min): 63 dB
• Input Offset Voltage: 8 mV
• Operating Supply Voltage: 3 V, 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: Details

4.0
The MCP631/2/3/5 family op amps is manufactured
using Microchip’s state of the art CMOS process. It is
designed for low cost, low power and high speed
applications. Its low supply voltage, low quiescent
current and wide bandwidth make the MCP631/2/3/5
ideal for battery-powered applications.
4.1
4.1.1
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages.
exceeding both supplies with no phase inversion.
4.1.2
The ESD protection on the inputs can be depicted as
shown in
protect the input transistors, and to minimize input bias
current (I
when they try to go more than one diode drop below
V
above V
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
FIGURE 4-1:
Structures.
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Section 1.1
“Absolute Maximum Ratings †”).
the recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins
(V
the resistors R
out of the input pins. Diodes D
input pins (V
V
implemented as shown, resistors R
the current through D
© 2009 Microchip Technology Inc.
SS
DD
IN
. They also clamp any voltages that go too far
+ and V
, and dump any currents onto V
V
V
V
IN
DD
SS
+
DD
APPLICATIONS
Input
B
). The input ESD diodes clamp the inputs
Figure
; their breakdown voltage is high enough to
Figure 2-38
Bond
Bond
Bond
PHASE REVERSAL
INPUT VOLTAGE AND CURRENT
LIMITS
IN
Pad
Pad
Pad
IN
–) from going too far below ground, and
1
+ and V
and R
4-1. This structure was chosen to
1
2
Simplified Analog Input ESD
and D
limit the possible current drawn
IN
Stage
Input
–) from going too far above
shows
2
.
1
and D
an
1
Figure 4-2
and R
Bond
Pad
input
2
prevent the
DD
2
V
also limit
. When
IN
voltage
shows
–
FIGURE 4-2:
Inputs.
It is also possible to connect the diodes to the left of the
resistor R
the diodes D
mechanism. The resistors then serve as in-rush
current limiters; the DC current into the input pins
(V
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (V
Figure
need to limit the usable voltage range.
4.1.3
The input stage of the MCP631/2/3/5 op amps uses a
differential
low common mode input voltages (V
between V
operation, the input offset voltage (V
at both
See
When operating at very low non-inverting gains, the
output voltage is limited at the top by the V
(< V
FIGURE 4-3:
Limitations for Linear Operation.
IN
+ and V
DD
Figure 2-5
V
V
2-13. Applications that are high impedance may
– 1.3V); see
1
2
R
R
1
SS
1
2
V
V
and R
NORMAL OPERATION
IN
1
>
>
PMOS
IN
V
CM
R
R
– 0.3V and V
–) should be very small.
and D
SS
V
V
D
1
2
and
SS
SS
= V
<
1
2
CM
V
MCP631/2/3/5
. In this case, the currents through
– (minimum expected V
– (minimum expected V
SS
Figure 2-6
IN
2
Figure
) is below ground (V
need to be limited by some other
input
,
V
Protecting the Analog
Unity Gain Voltage
– 0.3V
V
DD
OUT
D
2
DD
MCP63X
2 mA
2 mA
4-3.
V
≤
stage.
– 1.3V. To ensure proper
DD
V
for temperature effects.
DD
MCP63X
and
–
DS22197A-page 21
1.3V
It
OS
V
CM
OUT
) is measured
operates
), with V
V
V
1
2
)
)
DD
OUT
CM
SS
– 1.3V.
); see
range
CM
at