PIC12F635T-I/MD Microchip Technology, PIC12F635T-I/MD Datasheet - Page 143
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PIC12F635T-I/MD
Manufacturer Part Number
PIC12F635T-I/MD
Description
1.75 KB Flash, 64 RAM, 6 I/O 8 DFN 4x4mm T/R
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Specifications of PIC12F635T-I/MD
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
5
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164326 - MODULA SKT PM3 20QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFNXLT08DFN - SOCKET TRANSITION ICE 8DFN
Data Converters
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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FIGURE 12-8:
TABLE 12-6:
© 2007 Microchip Technology Inc.
INTCON
IOCA
PIR1
PIE1
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’, q = value depends upon condition.
Note 1:
Instruction Flow
Note 1: INTF flag is sampled here (every Q1).
Name
OSC1
CLKOUT
INT pin
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
PC
Instruction
Fetched
Instruction
Executed
2: Asynchronous interrupt latency = 3-4 T
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 15.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
Shaded cells are not used by the Interrupt module.
PIC16F636/639 only.
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
(3)
Bit 7
EEIF
EEIE
GIE
—
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Q1
Inst (PC – 1)
(1)
INT PIN INTERRUPT TIMING
Inst (PC)
LVDIF
LVDIE
Q2
Bit 6
PEIE
PC
—
Q3
(4)
IOCA5
Q4
CRIF
CRIE
(5)
Bit 5
T0IE
Q1
Inst (PC + 1)
C2IF
C2IE
IOCA4 IOCA3 IOCA2
Bit 4
INTE
Q2
(1)
Inst (PC)
PC + 1
CY
(1)
(1)
Q3
. Synchronous latency = 3 T
PIC12F635/PIC16F636/639
RAIE
Bit 3
C1IF
C1IE
Q4
Interrupt Latency
Q1
OSFIE
Dummy Cycle
OSFIF
Bit 2
T0IF
Q2
PC + 1
—
Q3
IOCA1
INTF
Bit 1
(2)
Q4
—
—
CY
, where T
Q1
Dummy Cycle
Inst (0004h)
TMR1IF 0000 00-0 0000 00-0
TMR1IE 0000 00-0 0000 00-0
IOCA0
Q2
RAIF
Bit 0
0004h
CY
= instruction cycle time. Latency
Q3
0000 000x 0000 000x
--00 0000 --00 0000
POR, BOR
Q4
Value on:
Q1
DS41232D-page 141
Inst (0005h)
Inst (0004h)
Q2
0005h
Value on
all other
Q3
Resets
Q4
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